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Date: Tue, 8 Aug 2023 07:57:19 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Jie Luo <quic_luoj@...cinc.com>, agross@...nel.org,
andersson@...nel.org, konrad.dybcio@...aro.org,
mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
p.zabel@...gutronix.de
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
quic_srichara@...cinc.com
Subject: Re: [PATCH 2/3] dt-bindings: clock: add qca8386/qca8084 clock and
reset definitions
On 08/08/2023 07:19, Jie Luo wrote:
>>> +properties:
>>> + compatible:
>>> + const: qcom,nsscc-qca8k
>>
>> SoC name is before IP block names. See:
>> Documentation/devicetree/bindings/arm/qcom-soc.yaml
>>
>> qca8k is not SoC specific. I don't know what you are documenting here,
>> but if this is a SoC, then follow SoC rules.
>>
>> If this is not SoC, it confuses me a bit to use GCC binding.
>>
>> Anyway, this was not tested, as pointed out by bot... Please test the
>> code before sending.
>>
>> Best regards,
>> Krzysztof
>>
>
> Hi Krzysztof,
>
> Thanks for the review comments.
> qca8383/qca8084 is a network chip that support switch mode and PHY mode,
> the hardware register is accessed by MDIO bus, which is not a SOC.
>
> But it has the self-contained clock controller system, the clock
> framework of qca8386/qca8084 is same as the GCC of ipq platform such as
> ipq9574.
OK
>
> would you help advise whether we can document it with the compatible
> "qcom,qca8k-nsscc"?
For example:
qcom,qca8084-nsscc
Best regards,
Krzysztof
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