[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230809190943.unpcbrinyn5ppei7@hydrated>
Date: Wed, 9 Aug 2023 14:09:43 -0500
From: Nishanth Menon <nm@...com>
To: Apurva Nandan <a-nandan@...com>
CC: Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <kristo@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Rafael J Wysocki <rafael@...nel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Amit Kucheria <amitk@...nel.org>,
Zhang Rui <rui.zhang@...el.com>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-pm@...r.kernel.org>, Udit Kumar <u-kumar1@...com>,
Keerthy J <j-keerthy@...com>
Subject: Re: [PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported
frequencies for A72
On 23:09-20230809, Apurva Nandan wrote:
> From: Keerthy <j-keerthy@...com>
>
> Add 750M, 1G, 1.5G & 2G as the supported frequencies for A72.
> This enables support for Dynamic Frequency Scaling(DFS)
>
> Signed-off-by: Keerthy <j-keerthy@...com>
> Signed-off-by: Apurva Nandan <a-nandan@...com>
> ---
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> index ef73e6d7e858..7222c453096f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> @@ -48,6 +48,10 @@ cpu0: cpu@0 {
> d-cache-line-size = <64>;
> d-cache-sets = <256>;
> next-level-cache = <&L2_0>;
> + clocks = <&k3_clks 202 2>;
> + clock-names = "cpu";
> + operating-points-v2 = <&cpu0_opp_table>;
> + #cooling-cells = <2>; /* min followed by max */
> };
>
> cpu1: cpu@1 {
> @@ -62,6 +66,30 @@ cpu1: cpu@1 {
> d-cache-line-size = <64>;
> d-cache-sets = <256>;
> next-level-cache = <&L2_0>;
> + clocks = <&k3_clks 203 0>;
> + clock-names = "cpu";
> + operating-points-v2 = <&cpu0_opp_table>;
> + #cooling-cells = <2>; /* min followed by max */
> + };
> + };
> +
> + cpu0_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp4-2000000000 {
> + opp-hz = /bits/ 64 <2000000000>;
> + };
> +
> + opp3-1500000000 {
> + opp-hz = /bits/ 64 <1500000000>;
> + };
> +
> + opp2-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + };
> +
> + opp1-750000000 {
> + opp-hz = /bits/ 64 <750000000>;
> };
> };
>
> --
> 2.34.1
>
Are you sure this is correct to enable all OPPs without efuse bit checks?
https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
7.5 Operating Performance Points
DRA821xC operates only upto 750MHz
DRA821xE at 1GHz
DRA821xL upto 1.5GHz and
DRA821xT upto 2GHz
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Powered by blists - more mailing lists