linux-kernel - Re: [PATCH 2/4] clk: qcom: branch: Add mem ops support for branch2 clocks

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Message-ID: <1e8fb9ba-9b18-487d-aa2e-4b246ae5b352@linaro.org>
Date:   Wed, 9 Aug 2023 21:59:41 +0200
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Imran Shaik <quic_imrashai@...cinc.com>,
        Andy Gross <agross@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>
Cc:     Taniya Das <quic_tdas@...cinc.com>, linux-arm-msm@...r.kernel.org,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Ajit Pandey <quic_ajipan@...cinc.com>,
        Jagadeesh Kona <quic_jkona@...cinc.com>
Subject: Re: [PATCH 2/4] clk: qcom: branch: Add mem ops support for branch2
 clocks

On 8.08.2023 07:14, Imran Shaik wrote:
> From: Taniya Das <quic_tdas@...cinc.com>
> 
> Clock CBCRs with memories need an update for memory before enable/disable
> of the clock. Add support for the mem ops to handle this sequence.
> 
> Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
> Signed-off-by: Imran Shaik <quic_imrashai@...cinc.com>
> ---
>  drivers/clk/qcom/clk-branch.c | 38 +++++++++++++++++++++++++++++++++++
>  drivers/clk/qcom/clk-branch.h |  4 ++++
>  2 files changed, 42 insertions(+)
> 
> diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
> index fc4735f74f0f..95ffcd380039 100644
> --- a/drivers/clk/qcom/clk-branch.c
> +++ b/drivers/clk/qcom/clk-branch.c
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /*
>   * Copyright (c) 2013, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
>   */
>  
>  #include <linux/kernel.h>
> @@ -134,6 +135,43 @@ static void clk_branch2_disable(struct clk_hw *hw)
>  	clk_branch_toggle(hw, false, clk_branch2_check_halt);
>  }
>  
> +static int clk_branch2_mem_enable(struct clk_hw *hw)
> +{
> +	struct clk_branch *br = to_clk_branch(hw);
> +	u32 val;
> +	int count = 200;
> +
> +	regmap_update_bits(br->clkr.regmap, br->mem_enable_reg,
> +			br->mem_enable_ack_bit, br->mem_enable_ack_bit);
> +
> +	regmap_read(br->clkr.regmap, br->mem_ack_reg, &val);
> +
> +	while (count-- > 0) {
> +		if (val & br->mem_enable_ack_bit)
One more comment, since the variable is named "ack bit", perhaps the
value within could be a bit number and you could use BIT() here.

Otherwise with you having chosen u8 for the type, there's not a whole
lot of flexibility.

Konrad