linux-kernel - RE: [PATCH v2 4/5] net: hpe: Add GXP UMAC Driver

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Message-ID: <DM4PR84MB19277DFEB543CF29AB3D58608812A@DM4PR84MB1927.NAMPRD84.PROD.OUTLOOK.COM>
Date:   Wed, 9 Aug 2023 23:55:48 +0000
From:   "Hawkins, Nick" <nick.hawkins@....com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     "christophe.jaillet@...adoo.fr" <christophe.jaillet@...adoo.fr>,
        "simon.horman@...igine.com" <simon.horman@...igine.com>,
        "Verdun, Jean-Marie" <verdun@....com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "conor+dt@...nel.org" <conor+dt@...nel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 4/5] net: hpe: Add GXP UMAC Driver

> > > So what you call a PHY is probably a PCS. Please look at the API used
> > > in driver/net/pcs/. The real PHYs are external.
> > 
> > I doubled checked the internal PHY is considered a PHY, but I believe
> > I can represent it as a PCS.

Hi Andrew,

Thank you for the additional information.

> Is there proper documentation somewhere? register set? Is there
> registers to kick off Base1000X/SGMII auto-neg? Somewhere to get the
> results of the auto-neg? Since this is Base1000X/SGMII you want to
> know if the link between it and the external PHY has established. And
> if there is not an external PHY, but an SFP, this auto neg is with the
> link peer, not the PHY. If it follows 802.3 clause 37, there should
> already be a lot of helper code for you. Is this is licensed core?

After discussing with the ASIC team:
The vendor IP in our ASIC performs a parallel GMII to serial SGMII
translation, including clock recovery and framing. It implements
the entire IEEE 802.3z PCS and is managed with a MCD/MDIO
serial interface. The SGMII interface connects to an external PHY
(and the external PHY is managed with a separate MDIO interface).

Thanks,

-Nick Hawkins