linux-kernel - Re: [PATCH v1 2/4] dt-bindings: clock: add qca8386/qca8084 clock and reset definitions

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Message-ID: <7d52cff6-a175-5925-a4c6-087f5de153b2@quicinc.com>
Date:   Thu, 10 Aug 2023 11:51:58 +0800
From:   Jie Luo <quic_luoj@...cinc.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        <andersson@...nel.org>, <agross@...nel.org>,
        <konrad.dybcio@...aro.org>, <mturquette@...libre.com>,
        <sboyd@...nel.org>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
        <catalin.marinas@....com>, <will@...nel.org>,
        <p.zabel@...gutronix.de>
CC:     <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <quic_srichara@...cinc.com>
Subject: Re: [PATCH v1 2/4] dt-bindings: clock: add qca8386/qca8084 clock and
 reset definitions



On 8/9/2023 11:34 PM, Krzysztof Kozlowski wrote:
> On 09/08/2023 10:00, Luo Jie wrote:
>> QCA8386/QCA8084 includes the clock & reset controller that is
>> accessed by MDIO bus. Two work modes are supported, qca8386 works
>> as switch mode, qca8084 works as PHY mode.
>>
>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>> ---
> 
> Thank you for your patch. There is something to discuss/improve.
> 
>> +
>> +properties:
>> +  compatible:
>> +    oneOf:
>> +      - const: qcom,qca8084-nsscc
>> +      - items:
>> +          - enum:
>> +              - qcom,qca8085-nsscc
>> +              - qcom,qca8082-nsscc
>> +              - qcom,qca8386-nsscc
>> +              - qcom,qca8385-nsscc
>> +              - qcom,qca8384-nsscc
> 
> Please keep this enum sorder alphanumerically.

Okay, will update this in the next patch set.

> 
>> +          - const: qcom,qca8084-nsscc
>> +
>> +  clocks:
>> +    items:
>> +      - description: Chip XO source
>> +      - description: UNIPHY0 RX 312P5M/125M clock source
>> +      - description: UNIPHY0 TX 312P5M/125M clock source
>> +      - description: UNIPHY1 RX 312P5M/125M clock source
>> +      - description: UNIPHY1 TX 312P5M/125M clock source
>> +      - description: UNIPHY1 RX 312P5M clock source
>> +      - description: UNIPHY1 TX 312P5M clock source
>> +
>> +  reg:
>> +    items:
>> +      - description: MDIO bus address for Clock & Reset Controller register
>> +
>> +required:
>> +  - compatible
>> +  - clocks
>> +  - reg
>> +
>> +allOf:
>> +  - $ref: qcom,gcc.yaml#
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    mdio {
>> +      #address-cells = <1>;
>> +      #size-cells = <0>;
>> +
>> +      clock-controller@...000 {
>> +        compatible = "qcom,qca8084-nsscc";
>> +        reg = <24>;
> 
> I think changes from your previous version... Unit address must match
> it, so clock-controller@24

okay, will use the clock-controller@24 in the next patch set, thanks.

> 
> 
>> +        clocks = <&qca8k_xo>,
>> +                 <&qca8k_uniphy0_rx>,
> 
> 
> Best regards,
> Krzysztof
>