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Message-ID: <8189905f-861d-371e-52f8-6953e928262a@quicinc.com>
Date: Thu, 10 Aug 2023 12:51:33 +0800
From: Jie Luo <quic_luoj@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
<andersson@...nel.org>, <agross@...nel.org>,
<konrad.dybcio@...aro.org>, <mturquette@...libre.com>,
<sboyd@...nel.org>, <robh+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <conor+dt@...nel.org>,
<catalin.marinas@....com>, <will@...nel.org>,
<p.zabel@...gutronix.de>
CC: <linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_srichara@...cinc.com>
Subject: Re: [PATCH v1 0/4] add clock controller of qca8386/qca8084
On 8/9/2023 11:32 PM, Krzysztof Kozlowski wrote:
> On 09/08/2023 10:00, Luo Jie wrote:
>> qca8xxx is 4 * 2.5GBaseT ports chip, working as switch mode
>> named by qca8386, or working as PHY mode named by qca8084,
>> clock hardware reigster is accessed by MDIO bus.
>>
>> This patch series add the clock controller of qca8363/qca8084,
>> and add the clock ops clk_branch2_qca8k_ops to avoid spin lock
>> used during the clock operation of qca8k clock controller where
>> the sleep happens when accessing clock control register by MDIO
>> bus.
>>
>> Changes in v1:
>> * remove clock flag CLK_ENABLE_MUTEX_LOCK.
>> * add clock ops clk_branch2_qca8k_ops.
>> * improve yaml file for fixing dtschema warnings.
>> * enable clock controller driver in defconfig.
>
> So this is v2, not v1. Your next version, if happens, will be v3, please.
>
> Best regards,
> Krzysztof
>
got it, i will use V3 in the next patch set, thanks Krzysztof.
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