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Message-ID: <bfc2eb22-54af-dab8-72e3-a142470590c3@intel.com>
Date: Thu, 10 Aug 2023 09:31:41 +0800
From: Tina Zhang <tina.zhang@...el.com>
To: "Tian, Kevin" <kevin.tian@...el.com>,
Jason Gunthorpe <jgg@...pe.ca>,
"Lu Baolu" <baolu.lu@...ux.intel.com>,
Michael Shavit <mshavit@...gle.com>
CC: "iommu@...ts.linux.dev" <iommu@...ts.linux.dev>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/5] Share sva domains with all devices bound to a mm
Hi,
On 8/9/23 17:41, Tian, Kevin wrote:
>> From: Zhang, Tina <tina.zhang@...el.com>
>> Sent: Tuesday, August 8, 2023 3:50 PM
>>
>> A sva domain's lifetime begins with binding a device to a mm and ends
>> by releasing all the bound devices from that sva domain. Technically,
>> there could be more than one sva domain identified by the mm PASID for
>> the use of bound devices issuing DMA transactions.
>
> Could you elaborate it with some concrete examples which motivate
> this change?
The motivation is to remove the superfluous IOTLB invalidation in
current VT-d driver.
Currently, in VT-d driver, due to lacking shared sva domain info, in
intel_flush_svm_range(), both iotlb and dev-tlb invalidation operations
are performed per-device. However, difference devices could be behind
one IOMMU (e.g., four devices are behind one IOMMU) and invoking iotlb
per-device gives us more iotlb invalidation than necessary (4 iotlb
invalidation instead of 1). This issue may give more performance impact
when in a virtual machine guest, as currently we have one virtual VT-d
for in front of those virtual devices.
This patch fixes this issue by attaching shared sva domain information
to mm, so that it can be utilized in the mm_notifier_ops callbacks.
Regards,
-Tina
>
>>
>> To support mm PASID 1:n with sva domains, each mm needs to keep both a
>> reference list of allocated sva domains and the corresponding PASID.
>> However, currently, mm struct only has one pasid field for sva usage,
>> which is used to keep the info of an assigned PASID. That pasid field
>> cannot provide sufficient info to build up the 1:n mapping between PASID
>> and sva domains.
>>
>> This patch-set fills the gap by adding an mm_iommu field[1], whose type is
>> mm_iommu_data struct, to replace the old pasid field. The introduced
>> mm_iommu_data struct keeps info of both a reference list of sva domains
>> and an assigned PASID.
>>
>>
>> [1]: https://lore.kernel.org/linux-iommu/ZIBxPd1%2FJCAle6yP@nvidia.com/
>>
>>
>> The RFC version of this patch-set is here:
>> https://lore.kernel.org/linux-iommu/20230707013441.365583-1-
>> tina.zhang@...el.com/
>>
>> Tina Zhang (5):
>> iommu: Add mm_get_pasid() helper function
>> iommu: Call helper function to get assigned pasid value
>> mm: Add structure to keep sva information
>> iommu: Support mm PASID 1:n with sva domains
>> mm: Deprecate pasid field
>>
>> arch/x86/kernel/traps.c | 2 +-
>> .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 12 ++---
>> drivers/iommu/intel/svm.c | 8 +--
>> drivers/iommu/iommu-sva.c | 50 ++++++++++++-------
>> include/linux/iommu.h | 19 +++++--
>> include/linux/mm_types.h | 3 +-
>> kernel/fork.c | 1 -
>> mm/init-mm.c | 3 --
>> 8 files changed, 58 insertions(+), 40 deletions(-)
>>
>> --
>> 2.17.1
>
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