| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Thu, 10 Aug 2023 17:06:18 +0530
From: "Alim Akhtar" <alim.akhtar@...sung.com>
To: "'Krzysztof Kozlowski'" <krzysztof.kozlowski@...aro.org>,
"'Sylwester Nawrocki'" <s.nawrocki@...sung.com>,
"'Tomasz Figa'" <tomasz.figa@...il.com>,
"'Chanwoo Choi'" <cw00.choi@...sung.com>,
"'Michael Turquette'" <mturquette@...libre.com>,
"'Stephen Boyd'" <sboyd@...nel.org>,
"'Rob Herring'" <robh+dt@...nel.org>,
"'Conor Dooley'" <conor+dt@...nel.org>,
<linux-samsung-soc@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: RE: [PATCH 09/11] clk: samsung: exynos850: do not define number of
clocks in bindings
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>; Sylwester
> Nawrocki <s.nawrocki@...sung.com>; Tomasz Figa
> <tomasz.figa@...il.com>; Chanwoo Choi <cw00.choi@...sung.com>; Alim
> Akhtar <alim.akhtar@...sung.com>; Michael Turquette
> <mturquette@...libre.com>; Stephen Boyd <sboyd@...nel.org>; Rob
> Herring <robh+dt@...nel.org>; Conor Dooley <conor+dt@...nel.org>;
> linux-samsung-soc@...r.kernel.org; linux-clk@...r.kernel.org; linux-arm-
> kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> devicetree@...r.kernel.org
> Subject: [PATCH 09/11] clk: samsung: exynos850: do not define number of
> clocks in bindings
>
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously. Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
>
> Define number of clocks per each clock controller inside the driver
directly.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@...sung.com>
> drivers/clk/samsung/clk-exynos850.c | 35 ++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos850.c
b/drivers/clk/samsung/clk-
> exynos850.c
> index c32b2e6451a0..bdc1eef7d6e5 100644
> --- a/drivers/clk/samsung/clk-exynos850.c
> +++ b/drivers/clk/samsung/clk-exynos850.c
> @@ -16,6 +16,19 @@
> #include "clk.h"
> #include "clk-exynos-arm64.h"
>
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH +
> 1)
> +#define CLKS_NR_APM
> (CLK_GOUT_SYSREG_APM_PCLK + 1)
> +#define CLKS_NR_AUD
> (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
> +#define CLKS_NR_CMGP
> (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
> +#define CLKS_NR_G3D
> (CLK_GOUT_G3D_SYSREG_PCLK + 1)
> +#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK +
> 1)
> +#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
> +#define CLKS_NR_MFCMSCL
> (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
> +#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
> +#define CLKS_NR_CORE
> (CLK_GOUT_SYSREG_CORE_PCLK + 1)
> +#define CLKS_NR_DPU
> (CLK_GOUT_DPU_SYSREG_PCLK + 1)
> +
> /* ---- CMU_TOP
------------------------------------------------------------- */
>
> /* Register Offset definitions for CMU_TOP (0x120e0000) */ @@ -485,7
> +498,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst
> = {
> .nr_div_clks = ARRAY_SIZE(top_div_clks),
> .gate_clks = top_gate_clks,
> .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
> - .nr_clk_ids = TOP_NR_CLK,
> + .nr_clk_ids = CLKS_NR_TOP,
> .clk_regs = top_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
> };
> @@ -625,7 +638,7 @@ static const struct samsung_cmu_info apm_cmu_info
> __initconst = {
> .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
> .fixed_clks = apm_fixed_clks,
> .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
> - .nr_clk_ids = APM_NR_CLK,
> + .nr_clk_ids = CLKS_NR_APM,
> .clk_regs = apm_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
> .clk_name = "dout_clkcmu_apm_bus",
> @@ -908,7 +921,7 @@ static const struct samsung_cmu_info aud_cmu_info
> __initconst = {
> .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
> .fixed_clks = aud_fixed_clks,
> .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
> - .nr_clk_ids = AUD_NR_CLK,
> + .nr_clk_ids = CLKS_NR_AUD,
> .clk_regs = aud_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
> .clk_name = "dout_aud",
> @@ -1011,7 +1024,7 @@ static const struct samsung_cmu_info
> cmgp_cmu_info __initconst = {
> .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
> .fixed_clks = cmgp_fixed_clks,
> .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
> - .nr_clk_ids = CMGP_NR_CLK,
> + .nr_clk_ids = CLKS_NR_CMGP,
> .clk_regs = cmgp_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
> .clk_name = "gout_clkcmu_cmgp_bus",
> @@ -1107,7 +1120,7 @@ static const struct samsung_cmu_info
> g3d_cmu_info __initconst = {
> .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
> .gate_clks = g3d_gate_clks,
> .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
> - .nr_clk_ids = G3D_NR_CLK,
> + .nr_clk_ids = CLKS_NR_G3D,
> .clk_regs = g3d_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
> .clk_name = "dout_g3d_switch",
> @@ -1209,7 +1222,7 @@ static const struct samsung_cmu_info hsi_cmu_info
> __initconst = {
> .nr_mux_clks = ARRAY_SIZE(hsi_mux_clks),
> .gate_clks = hsi_gate_clks,
> .nr_gate_clks = ARRAY_SIZE(hsi_gate_clks),
> - .nr_clk_ids = HSI_NR_CLK,
> + .nr_clk_ids = CLKS_NR_HSI,
> .clk_regs = hsi_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(hsi_clk_regs),
> .clk_name = "dout_hsi_bus",
> @@ -1341,7 +1354,7 @@ static const struct samsung_cmu_info is_cmu_info
> __initconst = {
> .nr_div_clks = ARRAY_SIZE(is_div_clks),
> .gate_clks = is_gate_clks,
> .nr_gate_clks = ARRAY_SIZE(is_gate_clks),
> - .nr_clk_ids = IS_NR_CLK,
> + .nr_clk_ids = CLKS_NR_IS,
> .clk_regs = is_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(is_clk_regs),
> .clk_name = "dout_is_bus",
> @@ -1450,7 +1463,7 @@ static const struct samsung_cmu_info
> mfcmscl_cmu_info __initconst = {
> .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
> .gate_clks = mfcmscl_gate_clks,
> .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
> - .nr_clk_ids = MFCMSCL_NR_CLK,
> + .nr_clk_ids = CLKS_NR_MFCMSCL,
> .clk_regs = mfcmscl_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
> .clk_name = "dout_mfcmscl_mfc",
> @@ -1625,7 +1638,7 @@ static const struct samsung_cmu_info
> peri_cmu_info __initconst = {
> .nr_div_clks = ARRAY_SIZE(peri_div_clks),
> .gate_clks = peri_gate_clks,
> .nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
> - .nr_clk_ids = PERI_NR_CLK,
> + .nr_clk_ids = CLKS_NR_PERI,
> .clk_regs = peri_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
> .clk_name = "dout_peri_bus",
> @@ -1732,7 +1745,7 @@ static const struct samsung_cmu_info
> core_cmu_info __initconst = {
> .nr_div_clks = ARRAY_SIZE(core_div_clks),
> .gate_clks = core_gate_clks,
> .nr_gate_clks = ARRAY_SIZE(core_gate_clks),
> - .nr_clk_ids = CORE_NR_CLK,
> + .nr_clk_ids = CLKS_NR_CORE,
> .clk_regs = core_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(core_clk_regs),
> .clk_name = "dout_core_bus",
> @@ -1806,7 +1819,7 @@ static const struct samsung_cmu_info
> dpu_cmu_info __initconst = {
> .nr_div_clks = ARRAY_SIZE(dpu_div_clks),
> .gate_clks = dpu_gate_clks,
> .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
> - .nr_clk_ids = DPU_NR_CLK,
> + .nr_clk_ids = CLKS_NR_DPU,
> .clk_regs = dpu_clk_regs,
> .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
> .clk_name = "dout_dpu",
> --
> 2.34.1
Powered by blists - more mailing lists