[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <a12b6d39-0e26-7bdc-4207-c767342ebcf6@foss.st.com>
Date: Thu, 10 Aug 2023 16:52:01 +0200
From: Alexandre TORGUE <alexandre.torgue@...s.st.com>
To: Jisheng Zhang <jszhang@...nel.org>,
"David S . Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Giuseppe Cavallaro <peppe.cavallaro@...com>,
Jose Abreu <joabreu@...opsys.com>
CC: <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH net-next v3 06/10] net: stmmac: xgmac: support per-channel
irq
On 8/9/23 18:50, Jisheng Zhang wrote:
> The IP supports per channel interrupt, add support for this usage case.
>
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> ---
> .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 ++
> .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 33 +++++++++++--------
> 2 files changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
> index 81cbb13a101d..12e1228ccf2a 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
> @@ -327,6 +327,8 @@
>
> /* DMA Registers */
> #define XGMAC_DMA_MODE 0x00003000
> +#define XGMAC_INTM GENMASK(13, 12)
> +#define XGMAC_INTM_MODE1 0x1
> #define XGMAC_SWR BIT(0)
> #define XGMAC_DMA_SYSBUS_MODE 0x00003004
> #define XGMAC_WR_OSR_LMT GENMASK(29, 24)
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
> index b5ba4e0cca55..ef25af92d6cc 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
> @@ -31,6 +31,13 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr,
> value |= XGMAC_EAME;
>
> writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);
> +
> + if (dma_cfg->perch_irq_en) {
> + value = readl(ioaddr + XGMAC_DMA_MODE);
> + value &= ~XGMAC_INTM;
> + value |= FIELD_PREP(XGMAC_INTM, XGMAC_INTM_MODE1);
> + writel(value, ioaddr + XGMAC_DMA_MODE);
> + }
> }
>
> static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv,
> @@ -365,20 +372,20 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv,
> }
>
> /* TX/RX NORMAL interrupts */
> - if (likely(intr_status & XGMAC_NIS)) {
No longer need to check NIS bit ?
> - if (likely(intr_status & XGMAC_RI)) {
> - u64_stats_update_begin(&rx_q->rxq_stats.syncp);
> - rx_q->rxq_stats.rx_normal_irq_n++;
> - u64_stats_update_end(&rx_q->rxq_stats.syncp);
> - ret |= handle_rx;
> - }
> - if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) {
> - u64_stats_update_begin(&tx_q->txq_stats.syncp);
> - tx_q->txq_stats.tx_normal_irq_n++;
> - u64_stats_update_end(&tx_q->txq_stats.syncp);
> - ret |= handle_tx;
> - }
> + if (likely(intr_status & XGMAC_RI)) {
> + u64_stats_update_begin(&rx_q->rxq_stats.syncp);
> + rx_q->rxq_stats.rx_normal_irq_n++;
> + u64_stats_update_end(&rx_q->rxq_stats.syncp);
> + ret |= handle_rx;
> + }
> + if (likely(intr_status & XGMAC_TI)) {
> + u64_stats_update_begin(&tx_q->txq_stats.syncp);
> + tx_q->txq_stats.tx_normal_irq_n++;
> + u64_stats_update_end(&tx_q->txq_stats.syncp);
> + ret |= handle_tx;
> }
> + if (unlikely(intr_status & XGMAC_TBU))
> + ret |= handle_tx;
>
> /* Clear interrupts */
> writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
Powered by blists - more mailing lists