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Date:   Fri, 11 Aug 2023 12:44:53 +0100
From:   Will Deacon <will@...nel.org>
To:     Dave Martin <Dave.Martin@....com>, Mark Brown <broonie@...nel.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Catalin Marinas <catalin.marinas@....com>
Cc:     kernel-team@...roid.com, Will Deacon <will@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] arm64/fpsimd: Only provide the length to cpufeature for xCR registers

On Mon, 31 Jul 2023 14:58:48 +0100, Mark Brown wrote:
> For both SVE and SME we abuse the generic register field comparison
> support in the cpufeature code as part of our detection of unsupported
> variations in the vector lengths available to PEs, reporting the maximum
> vector lengths via ZCR_EL1.LEN and SMCR_EL1.LEN.  Since these are
> configuration registers rather than identification registers the
> assumptions the cpufeature code makes about how unknown bitfields behave
> are invalid, leading to warnings when SME features like FA64 are enabled
> and we hotplug a CPU:
> 
> [...]

Applied to arm64 (for-next/cpufeature), thanks!

[1/1] arm64/fpsimd: Only provide the length to cpufeature for xCR registers
      https://git.kernel.org/arm64/c/01948b09edc3

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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