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Message-ID: <SN1PR18MB21262B71F310B0AF33C2D2EFDB11A@SN1PR18MB2126.namprd18.prod.outlook.com>
Date: Sat, 12 Aug 2023 13:51:00 +0000
From: Gowthami Thiagarajan <gthiagarajan@...vell.com>
To: Mark Rutland <mark.rutland@....com>
CC: "will@...nel.org" <will@...nel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Sunil Kovvuri Goutham <sgoutham@...vell.com>,
Bharat Bhushan <bbhushan2@...vell.com>,
George Cherian <gcherian@...vell.com>,
Linu Cherian <lcherian@...vell.com>
Subject: Re: [PATCH 3/6] perf/marvell : Odyssey LLC-TAD performance monitor
support
Hi,
> -----Original Message-----
> From: Mark Rutland <mark.rutland@....com>
> Sent: Friday, July 28, 2023 9:08 PM
> To: Gowthami Thiagarajan <gthiagarajan@...vell.com>
> Cc: will@...nel.org; linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org; Sunil Kovvuri
> Goutham <sgoutham@...vell.com>; Bharat Bhushan <bbhushan2@...vell.com>; George Cherian
> <gcherian@...vell.com>; Linu Cherian <lcherian@...vell.com>
> Subject: [EXT] Re: [PATCH 3/6] perf/marvell : Odyssey LLC-TAD performance monitor support
>
> External Email
>
> ----------------------------------------------------------------------
> On Fri, Jun 30, 2023 at 05:33:48PM +0530, Gowthami Thiagarajan wrote:
> > Each TAD provides eight 64-bit counters for monitoring
> > cache behavior.The driver always configures the same counter for
> > all the TADs. The user would end up effectively reserving one of
> > eight counters in every TAD to look across all TADs.
> > The occurrences of events are aggregated and presented to the user
> > at the end of running the workload. The driver does not provide a
> > way for the user to partition TADs so that different TADs are used for
> > different applications.
> >
> > The performance events reflect various internal or interface activities.
> > By combining the values from multiple performance counters, cache
> > performance can be measured in terms such as: cache miss rate, cache
> > allocations, interface retry rate, internal resource occupancy, etc.
> >
> > Each supported counter's event and formatting information is exposed
> > to sysfs at /sys/devices/tad/. Use perf tool stat command to measure
> > the pmu events. For instance:
> >
> > perf stat -e tad_hit_ltg,tad_hit_dtg <workload>
> >
> > Signed-off-by: Gowthami Thiagarajan <gthiagarajan@...vell.com>
>
> This generally looks ok; I have a few comments below.
>
> [...]
>
> > +static void tad_pmu_event_counter_stop(struct perf_event *event, int flags)
> > +{
> > + struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu);
> > + struct hw_perf_event *hwc = &event->hw;
> > + u32 counter_idx = hwc->idx;
> > + int tad_region;
> > +
> > + /* TAD()_PFC() stop counting on the write
> > + * which sets TAD()_PRF()[CNTSEL] == 0
> > + */
>
> Please fix the comment style.
>
> Likewise for all other instances within this file.
>
> [...]
Ack.
>
> > +static int tad_pmu_event_counter_add(struct perf_event *event, int flags)
> > +{
> > + struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu);
> > + struct hw_perf_event *hwc = &event->hw;
> > + int idx;
> > +
> > + /* Get a free counter for this event */
> > + idx = find_first_zero_bit(tad_pmu->counters_map, TAD_MAX_COUNTERS);
> > + if (idx == TAD_MAX_COUNTERS)
> > + return -EAGAIN;
> > +
> > + set_bit(idx, tad_pmu->counters_map);
> > +
> > + hwc->idx = idx;
> > + hwc->state = PERF_HES_STOPPED;
> > + tad_pmu->events[idx] = event;
> > +
> > + if (flags & PERF_EF_START)
> > + tad_pmu_event_counter_start(event, flags);
> > +
> > + return 0;
> > +}
> > +
> > +static int tad_pmu_event_init(struct perf_event *event)
> > +{
> > + struct tad_pmu *tad_pmu = to_tad_pmu(event->pmu);
> > +
> > + if (event->attr.type != event->pmu->type)
> > + return -ENOENT;
>
> Why is this not rejecting smapling events, as patch 1 does?
This is missed here. Will add the check for rejecting sampling events.
>
> > +
> > + if (!event->attr.disabled)
> > + return -EINVAL;
>
> Why?
Just checks the default disabled attribute.
>
> > +
> > + if (event->state != PERF_EVENT_STATE_OFF)
> > + return -EINVAL;
>
> Event groups need to be verified here too.
>
> [...]
Ack. Will add the missed checks in the next version.
>
> > +static int tad_pmu_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct tad_region *regions;
> > + struct tad_pmu *tad_pmu;
> > + struct resource *res;
> > + u32 tad_pmu_page_size;
> > + u32 tad_page_size;
> > + u32 tad_cnt;
> > + int i, ret;
> > + char *name;
> > +
> > + tad_pmu = devm_kzalloc(&pdev->dev, sizeof(*tad_pmu), GFP_KERNEL);
> > + if (!tad_pmu)
> > + return -ENOMEM;
> > +
> > + platform_set_drvdata(pdev, tad_pmu);
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res) {
> > + dev_err(&pdev->dev, "Mem resource not found\n");
> > + return -ENODEV;
> > + }
> > +
> > + ret = device_property_read_u32(dev, "marvell,tad-page-size", &tad_page_size);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Can't find tad-page-size property\n");
> > + return ret;
> > + }
> > +
> > + ret = device_property_read_u32(dev, "marvell,tad-pmu-page-size",
> > + &tad_pmu_page_size);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Can't find tad-pmu-page-size property\n");
> > + return ret;
> > + }
>
> Why do you think these properties are necessary?
>
> These should almost certainly be provided by IO resources, and shouldn't need a
> custom property.
IO resources don't provide all the information in this case. Need to vary these values
at different boot times. So, kept these custom properties.
Thanks,
Gowthami
>
> Thanks,
> Mark.
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