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Message-ID: <20230813151253.38128-2-quic_jinlmao@quicinc.com>
Date: Sun, 13 Aug 2023 23:12:51 +0800
From: Mao Jinlong <quic_jinlmao@...cinc.com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
Mike Leach <mike.leach@...aro.org>,
James Clark <james.clark@....com>,
Leo Yan <leo.yan@...aro.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Andy Gross <agross@...nel.org>,
"Bjorn Andersson" <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
CC: Mao Jinlong <quic_jinlmao@...cinc.com>,
<coresight@...ts.linaro.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>,
Tingwei Zhang <quic_tingweiz@...cinc.com>,
Yuanfang Zhang <quic_yuanfang@...cinc.com>,
"Tao Zhang" <quic_taozha@...cinc.com>,
Hao Zhang <quic_hazha@...cinc.com>
Subject: [PATCH v2 1/3] Coresight: Add driver to support for CSR
This driver provides support for CoreSight Slave Register block
that hosts miscellaneous configuration registers. Those
configuration registers can be used to control, various coresight
configurations.
Signed-off-by: Hao Zhang <quic_hazha@...cinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@...cinc.com>
---
drivers/hwtracing/coresight/Kconfig | 12 ++
drivers/hwtracing/coresight/Makefile | 2 +
.../hwtracing/coresight/coresight-csr-core.c | 104 ++++++++++++++++++
drivers/hwtracing/coresight/coresight-csr.h | 32 ++++++
4 files changed, 150 insertions(+)
create mode 100644 drivers/hwtracing/coresight/coresight-csr-core.c
create mode 100644 drivers/hwtracing/coresight/coresight-csr.h
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 06f0a7594169..ddabab1e2516 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -247,4 +247,16 @@ config CORESIGHT_DUMMY
To compile this driver as a module, choose M here: the module will be
called coresight-dummy.
+
+config CORESIGHT_CSR
+ tristate "CoreSight Slave Register driver"
+ help
+ This driver provides support for CoreSight Slave Register block
+ that hosts miscellaneous configuration registers.
+ Those configuration registers can be used to control, various
+ coresight configurations.
+
+ To compile this driver as a module, choose M here: the module will be
+ called coresight-csr.
+
endif
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index 995d3b2c76df..6f8d17003ff7 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -31,3 +31,5 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
coresight-cti-sysfs.o
obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o
obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o
+obj-$(CONFIG_CORESIGHT_CSR) += coresight-csr.o
+coresight-csr-y := coresight-csr-core.o
diff --git a/drivers/hwtracing/coresight/coresight-csr-core.c b/drivers/hwtracing/coresight/coresight-csr-core.c
new file mode 100644
index 000000000000..e07070b650d3
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-csr-core.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+
+#include "coresight-priv.h"
+#include "coresight-csr.h"
+
+DEFINE_CORESIGHT_DEVLIST(csr_devs, "csr");
+
+static int csr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct coresight_platform_data *pdata;
+ struct csr_drvdata *drvdata;
+ struct resource *res;
+ struct coresight_desc desc = { 0 };
+
+ desc.name = coresight_alloc_device_name(&csr_devs, dev);
+ if (!desc.name)
+ return -ENOMEM;
+ pdata = coresight_get_platform_data(dev);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+ pdev->dev.platform_data = pdata;
+
+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+ drvdata->dev = &pdev->dev;
+ platform_set_drvdata(pdev, drvdata);
+
+ drvdata->clk = devm_clk_get(dev, "apb_pclk");
+ if (IS_ERR(drvdata->clk))
+ dev_dbg(dev, "csr not config clk\n");
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr-base");
+ if (!res)
+ return -ENODEV;
+ drvdata->pbase = res->start;
+
+ drvdata->base = devm_ioremap(dev, res->start, resource_size(res));
+ if (!drvdata->base)
+ return -ENOMEM;
+
+ desc.type = CORESIGHT_DEV_TYPE_HELPER;
+ desc.pdata = pdev->dev.platform_data;
+ desc.dev = &pdev->dev;
+
+ drvdata->csdev = coresight_register(&desc);
+ if (IS_ERR(drvdata->csdev))
+ return PTR_ERR(drvdata->csdev);
+
+ spin_lock_init(&drvdata->spin_lock);
+
+ dev_dbg(dev, "CSR initialized: %s\n", dev_name(dev));
+ return 0;
+}
+
+static int csr_remove(struct platform_device *pdev)
+{
+ struct csr_drvdata *drvdata = platform_get_drvdata(pdev);
+
+ coresight_unregister(drvdata->csdev);
+ return 0;
+}
+
+static const struct of_device_id csr_match[] = {
+ {.compatible = "qcom,coresight-csr"},
+ {}
+};
+
+static struct platform_driver csr_driver = {
+ .probe = csr_probe,
+ .remove = csr_remove,
+ .driver = {
+ .name = "coresight-csr",
+ .of_match_table = csr_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+static int __init csr_init(void)
+{
+ return platform_driver_register(&csr_driver);
+}
+module_init(csr_init);
+
+static void __exit csr_exit(void)
+{
+ platform_driver_unregister(&csr_driver);
+}
+module_exit(csr_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("CoreSight CSR driver");
diff --git a/drivers/hwtracing/coresight/coresight-csr.h b/drivers/hwtracing/coresight/coresight-csr.h
new file mode 100644
index 000000000000..b4fb947fe23b
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-csr.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CORESIGHT_CSR_H
+#define _CORESIGHT_CSR_H
+#include <linux/clk.h>
+#include <linux/coresight.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+/**
+ * struct csr_drvdata - specifics for the CSR device.
+ * @base: Memory mapped base address for this component.
+ * @pbase: Physical address base.
+ * @dev: The device entity associated to this component.
+ * @csdev: Data struct for coresight device.
+ * @clk: Clock of this component.
+ * @spin_lock: Spin lock for the data.
+ */
+struct csr_drvdata {
+ void __iomem *base;
+ phys_addr_t pbase;
+ struct device *dev;
+ struct coresight_device *csdev;
+ struct clk *clk;
+ spinlock_t spin_lock;
+};
+
+#endif
+
--
2.17.1
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