[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230814171406.214932-5-thippeswamy.havalige@amd.com>
Date: Mon, 14 Aug 2023 22:44:06 +0530
From: Thippeswamy Havalige <thippeswamy.havalige@....com>
To: <linux-kernel@...r.kernel.org>, <robh+dt@...nel.org>,
<bhelgaas@...gle.com>, <krzysztof.kozlowski@...aro.org>,
<linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<conor+dt@...nel.org>
CC: <lpieralisi@...nel.org>, <bharat.kumar.gogada@....com>,
<michal.simek@....com>, <linux-arm-kernel@...ts.infradead.org>,
"Thippeswamy Havalige" <thippeswamy.havalige@....com>
Subject: [PATCH v4 3/3] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
Our controller is expecting ECAM size to be programmed by software. By
programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB
ECAM region which is used to detect 16 buses, so by updating
"NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB
ECAM region to detect 256 buses.
Nothing will break, when having a DT with the smaller ECAM size and boot a
kernel that includes this change,but the kernel will only be able to use 16
buses.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@....com>
---
Changes in v4:
Move modified ECAM max size macro into a seperate patch.
drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 8fe0e8a325b0..e307aceba5c9 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -126,7 +126,7 @@
#define E_ECAM_CR_ENABLE BIT(0)
#define E_ECAM_SIZE_LOC GENMASK(20, 16)
#define E_ECAM_SIZE_SHIFT 16
-#define NWL_ECAM_MAX_SIZE 12
+#define NWL_ECAM_MAX_SIZE 16
#define CFG_DMA_REG_BAR GENMASK(2, 0)
#define CFG_PCIE_CACHE GENMASK(7, 0)
--
2.17.1
Powered by blists - more mailing lists