linux-kernel - Re: [PATCH 09/10] x86/virt/tdx: Wire up basic SEAMCALL functions

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Message-ID: <20230814203732.GC2257301@ls.amr.corp.intel.com>
Date:   Mon, 14 Aug 2023 13:37:32 -0700
From:   Isaku Yamahata <isaku.yamahata@...il.com>
To:     Yuan Yao <yuan.yao@...ux.intel.com>
Cc:     Isaku Yamahata <isaku.yamahata@...il.com>,
        "Huang, Kai" <kai.huang@...el.com>,
        "Hansen, Dave" <dave.hansen@...el.com>,
        "Christopherson,, Sean" <seanjc@...gle.com>,
        "bp@...en8.de" <bp@...en8.de>, "x86@...nel.org" <x86@...nel.org>,
        "peterz@...radead.org" <peterz@...radead.org>,
        "hpa@...or.com" <hpa@...or.com>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "Yamahata, Isaku" <isaku.yamahata@...el.com>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "sathyanarayanan.kuppuswamy@...ux.intel.com" 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>
Subject: Re: [PATCH 09/10] x86/virt/tdx: Wire up basic SEAMCALL functions

On Tue, Aug 08, 2023 at 05:16:06PM +0800,
Yuan Yao <yuan.yao@...ux.intel.com> wrote:

> On Thu, Jul 13, 2023 at 11:44:34AM -0700, Isaku Yamahata wrote:
> > On Thu, Jul 13, 2023 at 03:46:52AM +0000,
> > "Huang, Kai" <kai.huang@...el.com> wrote:
> >
> > > On Wed, 2023-07-12 at 15:15 -0700, Isaku Yamahata wrote:
> > > > > The SEAMCALL ABI is very similar to the TDCALL ABI and leverages much
> > > > > TDCALL infrastructure.  Wire up basic functions to make SEAMCALLs for
> > > > > the basic TDX support: __seamcall(), __seamcall_ret() and
> > > > > __seamcall_saved_ret() which is for TDH.VP.ENTER leaf function.
> > > >
> > > > Hi.  __seamcall_saved_ret() uses struct tdx_module_arg as input and output.  For
> > > > KVM TDH.VP.ENTER case, those arguments are already in unsigned long
> > > > kvm_vcpu_arch::regs[].  It's silly to move those values twice.  From
> > > > kvm_vcpu_arch::regs to tdx_module_args.  From tdx_module_args to real registers.
> > > >
> > > > If TDH.VP.ENTER is the only user of __seamcall_saved_ret(), can we make it to
> > > > take unsigned long kvm_vcpu_argh::regs[NR_VCPU_REGS]?  Maybe I can make the
> > > > change with TDX KVM patch series.
> > >
> > > The assembly code assumes the second argument is a pointer to 'struct
> > > tdx_module_args'.  I don't know how can we change __seamcall_saved_ret() to
> > > achieve what you said.  We might change the kvm_vcpu_argh::regs[NR_VCPU_REGS] to
> > > match 'struct tdx_module_args''s layout and manually convert part of "regs" to
> > > the structure and pass to __seamcall_saved_ret(), but it's too hacky I suppose.
> > >
> > > This was one concern that I mentioned VP.ENTER can be implemented by KVM in its
> > > own assembly in the TDX host v12 discussion.  I kinda agree we should leverage
> > > KVM's existing kvm_vcpu_arch::regs[NR_CPU_REGS] infrastructure to minimize the
> > > code change to the KVM's common infrastructure.  If so, I guess we have to carry
> > > this memory copy burden between two structures.
> > >
> > > Btw, I do find KVM's VP.ENTER code is a little bit redundant to the common
> > > SEAMCALL assembly, which is a good reason for KVM to use __seamcall() variants
> > > for TDH.VP.ENTER.
> > >
> > > So it's a tradeoff I think.
> > >
> > > On the other hand, given CoCo VMs normally don't expose all GPRs to VMM, it's
> > > also debatable whether we should invent another infrastructure to the KVM code
> > > to handle register access of CoCo VMs too, e.g., we can catch bugs easily when
> > > KVM tries to access the registers that it shouldn't access.
> >
> > Yes, we'd like to save/restore GPRs only for TDVMCALL. Otherwise skip
> > save/restore.
> 
> And another case to save/restore GPRs: supports DEBUG TD,
> which is type of TD guest allows VMM to change its register
> context, for debugging purpose.

For Debug TD case, we can use TDH.VP.RD(general purpose register) specifically.
We don't need to optimize for Debug TD case.
-- 
Isaku Yamahata <isaku.yamahata@...il.com>