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Message-Id: <1691991767-15809-5-git-send-email-hongxing.zhu@nxp.com>
Date: Mon, 14 Aug 2023 13:42:42 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: frank.li@....com, l.stach@...gutronix.de, shawnguo@...nel.org,
lpieralisi@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org
Cc: hongxing.zhu@....com, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, kernel@...gutronix.de,
linux-imx@....com
Subject: [PATCH v4 4/9] arm: dts: nxp: Add i.MX6QDL and i.MX6QP PCIe EP supports
Add i.MX6QDL and i.MX6QP PCIe EP supports.
Signed-off-by: Richard Zhu <hongxing.zhu@....com>
---
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 14 ++++++++++++++
arch/arm/boot/dts/nxp/imx/imx6qp.dtsi | 4 ++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
index bda182edc589..be02f7882c68 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
@@ -289,6 +289,20 @@ pcie: pcie@...c000 {
status = "disabled";
};
+ pcie_ep: pcie-ep@...c000 {
+ compatible = "fsl,imx6q-pcie-ep";
+ reg = <0x01ffc000 0x04000>, <0x01000000 0xf00000>;
+ reg-names = "dbi", "addr_space";
+ num-lanes = <1>;
+ clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
+ <&clks IMX6QDL_CLK_LVDS1_GATE>,
+ <&clks IMX6QDL_CLK_PCIE_REF_125M>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
+
aips1: bus@...0000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi
index fc164991d2ae..4ca53a4c254c 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi
@@ -118,3 +118,7 @@ &mmdc0 {
&pcie {
compatible = "fsl,imx6qp-pcie";
};
+
+&pcie_ep {
+ compatible = "fsl,imx6qp-pcie-ep";
+};
--
2.34.1
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