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Message-ID: <36dbb926-0694-f84b-44dc-9608537024b5@linaro.org>
Date: Mon, 14 Aug 2023 10:16:29 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Gowthami Thiagarajan <gthiagarajan@...vell.com>, will@...nel.org,
mark.rutland@....com, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
devicetree@...r.kernel.org
Cc: sgoutham@...vell.com, bbhushan2@...vell.com, lcherian@...vell.com
Subject: Re: [PATCH v2 6/6] dt-bindings: perf: Add Marvell Odyssey DDR PMU
On 12/08/2023 16:25, Gowthami Thiagarajan wrote:
> Add binding documentation for Marvell Odyssey DDR PMU.
>
> Signed-off-by: Gowthami Thiagarajan <gthiagarajan@...vell.com>
> ---
>
> v1->v2
> - No change
>
> .../devicetree/bindings/perf/marvell-cn10k-ddr.yaml | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
> index a18dd0a8c43a..a435cbf4aea0 100644
> --- a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
> +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml
> @@ -11,10 +11,15 @@ maintainers:
>
> properties:
> compatible:
> - items:
> + oneOf:
> - enum:
> - marvell,cn10k-ddr-pmu
> -
> + - marvell,odyssey-ddr-pmu
> + - items:
> + - enum:
> + - marvell,cn10k-ddr-pmu
> + - marvell,odyssey-ddr-pmu
> + - const: marvell,cn10k-ddr-pmu
This is absolutely bogus and does not make sense.
marvell,cn10k-ddr-pmu is not compatible with marvell,cn10k-ddr-pmu
Questions about actual name of SoC remain...
> reg:
> maxItems: 1
>
Best regards,
Krzysztof
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