linux-kernel - [PATCH] x86_64: Show CR4.PSE on auxiliaries like on BSP

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Message-ID: <103ad03a-8c93-c3e2-4226-f79af4d9a074@google.com>
Date:   Mon, 14 Aug 2023 19:53:18 -0700 (PDT)
From:   Hugh Dickins <hughd@...gle.com>
To:     Borislav Petkov <bp@...en8.de>
cc:     linux-kernel@...r.kernel.org, x86@...nel.org
Subject: [PATCH] x86_64: Show CR4.PSE on auxiliaries like on BSP

Set CR4.PSE in secondary_startup_64: the Intel SDM is clear that it does
not matter whether it's 0 or 1 when 4-level-pts are enabled, but it's
distracting to find CR4 different on BSP and auxiliaries - on x86_64,
BSP alone got to add the PSE bit, in probe_page_size_mask().

Signed-off-by: Hugh Dickins <hughd@...gle.com>
---
 arch/x86/kernel/head_64.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index c5b9289837dc..72e36739c407 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -181,8 +181,8 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
 	movl	$0, %ecx
 #endif
 
-	/* Enable PAE mode, PGE and LA57 */
-	orl	$(X86_CR4_PAE | X86_CR4_PGE), %ecx
+	/* Enable PAE mode, PSE, PGE and LA57 */
+	orl	$(X86_CR4_PAE | X86_CR4_PSE | X86_CR4_PGE), %ecx
 #ifdef CONFIG_X86_5LEVEL
 	testl	$1, __pgtable_l5_enabled(%rip)
 	jz	1f
-- 
2.35.3