linux-kernel - Re: [PATCH v6 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 15 Aug 2023 11:24:31 +0100
From:   Suzuki K Poulose <suzuki.poulose@....com>
To:     Ilkka Koskinen <ilkka@...amperecomputing.com>,
        Will Deacon <will@...nel.org>,
        Robin Murphy <robin.murphy@....com>,
        Besar Wicaksono <bwicaksono@...dia.com>,
        Jonathan Cameron <Jonathan.Cameron@...wei.com>,
        Mark Rutland <mark.rutland@....com>,
        Jonathan Corbet <corbet@....net>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-doc@...r.kernel.org
Subject: Re: [PATCH v6 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit
 writes

On 15/08/2023 07:35, Ilkka Koskinen wrote:
> Split the 64-bit register accesses if 64-bit access is not supported
> by the PMU.
> 
> Signed-off-by: Ilkka Koskinen <ilkka@...amperecomputing.com>
> Reviewed-by: Besar Wicaksono <bwicaksono@...dia.com>

Do we need a Fixes tag ?

With that:

Reviewed-by: Suzuki K Poulose <suzuki.poulose@....com>

Suzuki

> ---
>   drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c
> index 04be94b4aa48..6387cbad7a7d 100644
> --- a/drivers/perf/arm_cspmu/arm_cspmu.c
> +++ b/drivers/perf/arm_cspmu/arm_cspmu.c
> @@ -715,7 +715,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val)
>   	if (use_64b_counter_reg(cspmu)) {
>   		offset = counter_offset(sizeof(u64), event->hw.idx);
>   
> -		writeq(val, cspmu->base1 + offset);
> +		if (cspmu->has_atomic_dword)
> +			writeq(val, cspmu->base1 + offset);
> +		else
> +			lo_hi_writeq(val, cspmu->base1 + offset);


>   	} else {
>   		offset = counter_offset(sizeof(u32), event->hw.idx);
>