linux-kernel - [PATCH v1 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe

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Message-Id: <1692102408-7010-3-git-send-email-quic_krichai@quicinc.com>
Date:   Tue, 15 Aug 2023 17:56:47 +0530
From:   Krishna chaitanya chundru <quic_krichai@...cinc.com>
To:     manivannan.sadhasivam@...aro.org
Cc:     helgaas@...nel.org, linux-pci@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        quic_vbadigan@...cinc.com, quic_nitegupt@...cinc.com,
        quic_skananth@...cinc.com, quic_ramkri@...cinc.com,
        quic_parass@...cinc.com, krzysztof.kozlowski@...aro.org,
        Krishna chaitanya chundru <quic_krichai@...cinc.com>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
        DEVICE TREE BINDINGS)
Subject: [PATCH v1 2/3] arm64: dts: qcom: sm8450: Add opp table support to PCIe

PCIe needs to choose the appropriate performance state of RPMH power
domain based upon the PCIe gen speed.

So, let's add the OPP table support to specify RPMH performance states.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 595533a..681ea9c 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -381,6 +381,49 @@
 		};
 	};
 
+	pcie0_opp_table: opp-table-pcie0 {
+		compatible = "operating-points-v2";
+
+		opp-2500000 {
+			opp-hz = /bits/ 64 <2500000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+		};
+
+		opp-5000000 {
+			opp-hz = /bits/ 64 <5000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+		};
+
+		opp-8000000 {
+			opp-hz = /bits/ 64 <8000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+		};
+	};
+
+	pcie1_opp_table: opp-table-pcie1 {
+		compatible = "operating-points-v2";
+
+		opp-2500000 {
+			opp-hz = /bits/ 64 <2500000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+		};
+
+		opp-5000000 {
+			opp-hz = /bits/ 64 <5000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+		};
+
+		opp-8000000 {
+			opp-hz = /bits/ 64 <8000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+		};
+
+		opp-16000000 {
+			opp-hz = /bits/ 64 <16000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+		};
+	};
+
 	reserved_memory: reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -1803,6 +1846,8 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie0_default_state>;
 
+			operating-points-v2 = <&pcie0_opp_table>;
+
 			status = "disabled";
 		};
 
@@ -1915,6 +1960,8 @@
 			pinctrl-names = "default";
 			pinctrl-0 = <&pcie1_default_state>;
 
+			operating-points-v2 = <&pcie1_opp_table>;
+
 			status = "disabled";
 		};
 
-- 
2.7.4