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Message-ID: <20230815-certainly-sprang-209024530924@spud>
Date: Tue, 15 Aug 2023 15:19:55 +0100
From: Conor Dooley <conor@...nel.org>
To: Binbin Zhou <zhoubinbin@...ngson.cn>
Cc: Binbin Zhou <zhoubb.aaron@...il.com>,
Huacai Chen <chenhuacai@...ngson.cn>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Huacai Chen <chenhuacai@...nel.org>,
loongson-kernel@...ts.loongnix.cn, devicetree@...r.kernel.org,
Jiaxun Yang <jiaxun.yang@...goat.com>, diasyzhang@...cent.com,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: interrupt-controller: loongson,liointc: Fix
warnings about reg and interrupt description
Hey,
On Tue, Aug 15, 2023 at 04:47:13PM +0800, Binbin Zhou wrote:
> As we know, some Loongson-2K CPUs are single-core, e.g. Loongson-2K0500,
> and the "isr1" means routing interrupts to core1, which should be
> optional. So add maxItems/minItems limits to reg/reg-names.
> Also, The interrupt-names attribute represents a list of parent
> interrupt names that should change with interrupts.
This should have been with the other series that introduces the users
probably so that things make more sense to the reader.
> Signed-off-by: Binbin Zhou <zhoubinbin@...ngson.cn>
> ---
> .../interrupt-controller/loongson,liointc.yaml | 14 ++++++--------
> 1 file changed, 6 insertions(+), 8 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
> index 00b570c82903..adb428211a72 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
> @@ -11,7 +11,7 @@ maintainers:
>
> description: |
> This interrupt controller is found in the Loongson-3 family of chips and
> - Loongson-2K1000 chip, as the primary package interrupt controller which
> + Loongson-2K series chips, as the primary package interrupt controller which
> can route local I/O interrupt to interrupt lines of cores.
>
> allOf:
> @@ -33,6 +33,7 @@ properties:
> - const: main
> - const: isr0
> - const: isr1
> + minItems: 2
>
> interrupt-controller: true
>
> @@ -45,11 +46,9 @@ properties:
> interrupt-names:
> description: List of names for the parent interrupts.
> items:
> - - const: int0
> - - const: int1
> - - const: int2
> - - const: int3
> + pattern: int[0-3]
From a quick look at the new devicetrees, I don't understand the
ordering relaxation. Do you actually have a system that only has, for
example, int3?
Also, as the interrupt-names are not required, changing the ordering
here is not ABI compatible AFAICT. Does that have any fallout?
Thanks,
Conor.
> minItems: 1
> + maxItems: 4
>
> '#interrupt-cells':
> const: 2
> @@ -73,7 +72,6 @@ required:
> - '#interrupt-cells'
> - loongson,parent_int_map
>
> -
> unevaluatedProperties: false
>
> if:
> @@ -86,7 +84,8 @@ if:
> then:
> properties:
> reg:
> - minItems: 3
> + minItems: 2
> + maxItems: 3
>
> required:
> - reg-names
> @@ -113,7 +112,6 @@ examples:
> <0x0f000000>, /* int1 */
> <0x00000000>, /* int2 */
> <0x00000000>; /* int3 */
> -
> };
>
> ...
> --
> 2.39.3
>
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