linux-kernel - Re: [PATCH v2,1/2] mtd: spi-nor: giga: gd25lq64c: Disable quad mode according to bus width

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Message-ID: <CAJMQK-jgcH-OBQox3fisr0M0gbhFnSvKWCHwos2mtiRH7t8kVA@mail.gmail.com>
Date:   Thu, 17 Aug 2023 02:24:22 +0800
From:   Hsin-Yi Wang <hsinyi@...omium.org>
To:     Tudor Ambarus <tudor.ambarus@...aro.org>
Cc:     Michael Walle <michael@...le.cc>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Bjorn Andersson <andersson@...nel.org>,
        Pratyush Yadav <pratyush@...nel.org>,
        "Miquel Raynal )" <miquel.raynal@...tlin.com>,
        "Richard Weinberger )" <richard@....at>,
        "Vignesh Raghavendra )" <vigneshr@...com>,
        Rob Herring <robh+dt@...nel.org>,
        linux-mtd@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org,
        cros-qcom-dts-watchers@...omium.org,
        Andy Gross <agross@...nel.org>,
        Konrad Dybcio <konrad.dybcio@...aro.org>
Subject: Re: [PATCH v2,1/2] mtd: spi-nor: giga: gd25lq64c: Disable quad mode
 according to bus width

On Wed, Aug 16, 2023 at 8:34 PM Tudor Ambarus <tudor.ambarus@...aro.org> wrote:
>
>
>
> On 8/16/23 13:22, Michael Walle wrote:
> > Hi,
> >
> >>> like a fundamental problem and that commit 39d1e3340c73 ("mtd: spi-nor:
> >>> Fix clearing of QE bit on lock()/unlock()") is broken in that regard.
> >>
> >> what's wrong with the mentioned commit?
> >
> >         } else if (nor->params->quad_enable) {
> >                 /*
> >                  * If the Status Register 2 Read command (35h) is not
> >                  * supported, we should at least be sure we don't
> >                  * change the value of the SR2 Quad Enable bit.
> >                  *
> >                  * We can safely assume that when the Quad Enable method is
> >                  * set, the value of the QE bit is one, as a consequence of the
> >                  * nor->params->quad_enable() call.
> >                  *
> >                  * We can safely assume that the Quad Enable bit is present in
> >                  * the Status Register 2 at BIT(1). According to the JESD216
> >                  * revB standard, BFPT DWORDS[15], bits 22:20, the 16-bit
> >                  * Write Status (01h) command is available just for the cases
> >                  * in which the QE bit is described in SR2 at BIT(1).
> >                  */
> >                 sr_cr[1] = SR2_QUAD_EN_BIT1;
> >         } else {
> >                 sr_cr[1] = 0;
> >         }
> >
> > "We can safely assume that when the Quad Enable method..". We cannot, if we
> > don't have 4 I/O lines. The quad_enable is just the op how to do it, but not
> > *if* can do it. It seems to be missing the same check as the
> > spi_nor_quad_enable(). But I'm not sure if it's that simple.
> >
>
> I see. Then extending the if condition should do the trick, as
> spi_nor_write_16bit_sr_and_check() is called after setup. Something
> like:
>
> if (spi_nor_get_protocol_width(nor->read_proto) == 4 &&
>     spi_nor_get_protocol_width(nor->write_proto) == 4 &&
>     nor->params->quad_enable)
>
> Is this what Hsin-Yi is hitting?

Yes, it is. Adding these checks can solve the issue. The read out
width for both read and write is 1, which matches the default bus
width.

Thanks.