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Message-ID: <1a914071-d000-eaad-7941-30589f8e1da3@quicinc.com>
Date: Wed, 16 Aug 2023 14:20:55 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
<manivannan.sadhasivam@...aro.org>
CC: <helgaas@...nel.org>, <linux-pci@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<quic_vbadigan@...cinc.com>, <quic_nitegupt@...cinc.com>,
<quic_skananth@...cinc.com>, <quic_ramkri@...cinc.com>,
<quic_parass@...cinc.com>, Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>
Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: sm8450: Add opp table support to
PCIe
On 8/15/2023 6:01 PM, Krzysztof Kozlowski wrote:
> On 15/08/2023 14:26, Krishna chaitanya chundru wrote:
>> PCIe needs to choose the appropriate performance state of RPMH power
>> domain based upon the PCIe gen speed.
> This explanation should be also in bindings patch, otherwise why would
> we consider the bindings patch?
I will update binding patch with this information.
>
>> So, let's add the OPP table support to specify RPMH performance states.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 47 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index 595533a..681ea9c 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -381,6 +381,49 @@
>> };
>> };
>>
>> + pcie0_opp_table: opp-table-pcie0 {
>> + compatible = "operating-points-v2";
>> +
>> + opp-2500000 {
>> + opp-hz = /bits/ 64 <2500000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + };
>> +
>> + opp-5000000 {
>> + opp-hz = /bits/ 64 <5000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + };
>> +
>> + opp-8000000 {
>> + opp-hz = /bits/ 64 <8000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + };
>> + };
>> +
>> + pcie1_opp_table: opp-table-pcie1 {
>> + compatible = "operating-points-v2";
>> +
>> + opp-2500000 {
>> + opp-hz = /bits/ 64 <2500000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + };
>> +
>> + opp-5000000 {
>> + opp-hz = /bits/ 64 <5000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + };
>> +
>> + opp-8000000 {
>> + opp-hz = /bits/ 64 <8000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> + };
>> +
>> + opp-16000000 {
>> + opp-hz = /bits/ 64 <16000000>;
>> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>> + };
>> + };
>> +
>> reserved_memory: reserved-memory {
>> #address-cells = <2>;
>> #size-cells = <2>;
>> @@ -1803,6 +1846,8 @@
>> pinctrl-names = "default";
>> pinctrl-0 = <&pcie0_default_state>;
>>
>> + operating-points-v2 = <&pcie0_opp_table>;
> Why the table is not here? Is it shared with multiple devices?
I will move the table to here in the next patch.
- KC
>
> Best regards,
> Krzysztof
>
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