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Message-ID: <ZN+i1pEoN/NsWPKS@nvidia.com>
Date: Fri, 18 Aug 2023 13:56:54 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: Nicolin Chen <nicolinc@...dia.com>
Cc: "Liu, Yi L" <yi.l.liu@...el.com>,
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Subject: Re: [PATCH v4 09/12] iommu/vt-d: Add iotlb flush for nested domain
On Mon, Aug 14, 2023 at 11:18:46PM -0700, Nicolin Chen wrote:
> On Fri, Aug 11, 2023 at 09:45:21AM -0700, Nicolin Chen wrote:
>
> > > But if stepping back a bit supporting an array-based non-native format
> > > could simplify the uAPI design and allows code sharing for array among
> > > vendor drivers. You can still keep the entry as native format then the
> > > only difference with future in-kernel fast path is just on walking an array
> > > vs. walking a ring. And VMM doesn't need to expose non-invalidate
> > > cmds to the kernel and then be skipped.
> >
> > Ah, so we might still design the uAPI to be ring based at this
> > moment, yet don't support a case CONS > 0 to leave that to an
> > upgrade in the future.
> >
> > I will try estimating a bit how complicated to implement the
> > ring, to see if we could just start with that. Otherwise, will
> > just start with an array.
>
> I drafted a uAPI structure for a ring-based SW queue. While I am
> trying an implementation, I'd like to collect some comments at the
> structure, to see if it overall makes sense.
I don't think a ring makes alot of sense at this point. The only thing
it optimizes is a system call if the kernel needs to wrap around the
tail of the ring. It would possibly be better to have a small gather
list than try to describe the ring logic..
Further, the VMM already has to process it, so the vmm already knows
what ops are going to kernel are not. The VMM can just organize them
in a linear list in one way or another. We need to copy and read this
stuff in the VMM anyhow to protect against a hostile VM.
> One thing that I couldn't add to this common structure for SMMU
> is the hardware error code, which should be encoded in the higher
> bits of the consumer index register, following the SMMU spec:
> ERR, bits [30:24] Error reason code.
> - When a command execution error is detected, ERR is set to a
> reason code and then the SMMU_GERROR.CMDQ_ERR global error
> becomes active.
> - The value in this field is UNKNOWN when the CMDQ_ERR global
> error is not active. This field resets to an UNKNOWN value.
The invalidate ioctl should fail in some deterministic way and report
back the error code and the highest array index that maybe could have
triggered it.
The highest array index sounds generic, the error code maybe is too
Jason
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