lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 18 Aug 2023 08:54:28 -0500
From:   Mario Limonciello <mario.limonciello@....com>
To:     "Rafael J. Wysocki" <rafael@...nel.org>,
        David Laight <David.Laight@...lab.com>
Cc:     Mika Westerberg <mika.westerberg@...ux.intel.com>,
        Bjorn Helgaas <helgaas@...nel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        "linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
        Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>,
        Iain Lane <iain@...ngesquash.org.uk>,
        Shyam-sundar S-k <Shyam-sundar.S-k@....com>,
        "stable@...r.kernel.org" <stable@...r.kernel.org>
Subject: Re: [PATCH v13 01/12] PCI: Only put Intel PCIe ports >= 2015 into D3

On 8/18/2023 04:19, Rafael J. Wysocki wrote:
> On Fri, Aug 18, 2023 at 10:21 AM David Laight <David.Laight@...lab.com> wrote:
>>
>> From: Rafael J. Wysocki
>>> Sent: Friday, August 18, 2023 9:12 AM
>>>
>>> On Fri, Aug 18, 2023 at 7:14 AM Mario Limonciello
>>> <mario.limonciello@....com> wrote:
>>>>
>>>> commit 9d26d3a8f1b0 ("PCI: Put PCIe ports into D3 during suspend")
>>>> changed pci_bridge_d3_possible() so that any vendor's PCIe ports
>>>> from modern machines (>=2015) are allowed to be put into D3.
>>>>
>>>> Iain reports that USB devices can't be used to wake a Lenovo Z13
>>>> from suspend. This is because the PCIe root port has been put
>>>> into D3 and AMD's platform can't handle USB devices waking in this
>>>> case.
>>>>
>> ...
>>>> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
>>>> index 60230da957e0c..051e88ee64c63 100644
>>>> --- a/drivers/pci/pci.c
>>>> +++ b/drivers/pci/pci.c
>>>> @@ -3037,10 +3037,11 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge)
>>>>                          return false;
>>>>
>>>>                  /*
>>>> -                * It should be safe to put PCIe ports from 2015 or newer
>>>> +                * It is safe to put Intel PCIe ports from 2015 or newer
>>>>                   * to D3.
>>>>                   */
>>>
>>> I would say "Allow Intel PCIe ports from 2015 onward to go into D3 to
>>> achieve additional energy conservation on some platforms" without the
>>> "It is safe" part that is kind of obvious (it wouldn't be done if it
>>> were unsafe).
>>
>> Just say why...
>>
>> "Don't put root ports into D3 on non-Intel systems to avoid issues
>> with USB devices being unable to wake up some AMD based laptops."
> 
> Well, both pieces of information are actually useful: Why it is done
> on Intel systems in the first place and why it cannot be done on AMD
> systems.

Thanks guys, I'll add both in next version.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ