linux-kernel - Re: [PATCH 5/8] phy: exynos5-usbdrd: Add 26MHz ref clk support

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Message-ID: <e572cb3a-54bf-8f08-e74d-e1df42548b6a@linaro.org>
Date:   Sat, 19 Aug 2023 09:41:40 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Sam Protsenko <semen.protsenko@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Thinh Nguyen <Thinh.Nguyen@...opsys.com>
Cc:     JaeHun Jung <jh0801.jung@...sung.com>,
        Marek Szyprowski <m.szyprowski@...sung.com>,
        Sylwester Nawrocki <s.nawrocki@...sung.com>,
        Conor Dooley <conor+dt@...nel.org>,
        Vinod Koul <vkoul@...nel.org>,
        Kishon Vijay Abraham I <kishon@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Alim Akhtar <alim.akhtar@...sung.com>,
        Marc Kleine-Budde <mkl@...gutronix.de>,
        Heiko Stuebner <heiko@...ech.de>,
        linux-phy@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-samsung-soc@...r.kernel.org
Subject: Re: [PATCH 5/8] phy: exynos5-usbdrd: Add 26MHz ref clk support

On 19/08/2023 05:17, Sam Protsenko wrote:
> Modern Exynos chips (like Exynos850) might have 26 MHz OSCCLK external
> clock, which is also used as a PHY reference clock. For some USB PHY
> controllers (e.g USB DRD PHY block on Exynos850) there is no need to set
> the refclk frequency at all (and corresponding bits in CLKRSTCTRL[7:5]
> are marked RESERVED), so that value won't be set in the driver. But
> even in that case, 26 MHz support still has to be added, otherwise
> exynos5_rate_to_clk() fails, which leads in turn to probe error.
> 
> Add the correct value for 26MHz refclk to make it possible to add
> support for new Exynos USB DRD PHY controllers.
> 
> Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Best regards,
Krzysztof