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Message-Id: <20230821045216.641499-1-anshuman.khandual@arm.com>
Date: Mon, 21 Aug 2023 10:22:13 +0530
From: Anshuman Khandual <anshuman.khandual@....com>
To: linux-arm-kernel@...ts.infradead.org, suzuki.poulose@....com
Cc: Anshuman Khandual <anshuman.khandual@....com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Mike Leach <mike.leach@...aro.org>,
James Clark <james.clark@....com>,
Leo Yan <leo.yan@...aro.org>, Jonathan Corbet <corbet@....net>,
linux-doc@...r.kernel.org, coresight@...ts.linaro.org,
linux-kernel@...r.kernel.org
Subject: [PATCH V5 0/3] coresight: etm: Make cycle count threshold user configurable
This series makes ETM TRCCCCTRL based 'cc_threshold' user configurable via
the perf event attribute. But first, this implements an errata work around
affecting ETM TRCIDR3.CCITMIN value on certain cpus, overriding the field.
This series applies on v6.5-rc7.
Cc: Catalin Marinas <catalin.marinas@....com>
Cc: Will Deacon <will@...nel.org>
Cc: Suzuki K Poulose <suzuki.poulose@....com>
Cc: Mike Leach <mike.leach@...aro.org>
Cc: James Clark <james.clark@....com>
Cc: Leo Yan <leo.yan@...aro.org>
Cc: Jonathan Corbet <corbet@....net>
Cc: linux-doc@...r.kernel.org
Cc: coresight@...ts.linaro.org
Cc: linux-arm-kernel@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org
Changes in V5:
- Replaced 'where as' with single word 'whereas'
- Reworked 'cc_threshold' fallback to ETM_CYC_THRESHOLD_DEFAULT
Changes in V4:
https://lore.kernel.org/all/20230818112051.594986-1-anshuman.khandual@arm.com/
- Fixed a typo s/rangess/ranges,
- Renamed etm4_work_around_wrong_ccitmin() as etm4_core_reads_wrong_ccitmin()
- Moved drvdata->ccitmin value check for 256 inside etm4_core_reads_wrong_ccitmin()
- Moved the comment inside etm4_core_reads_wrong_ccitmin()
Changes in V3:
https://lore.kernel.org/all/20230811034600.944386-1-anshuman.khandual@arm.com/
- Added errata work around affecting TRCIDR3.CCITMIN
- Split the document update into a separate patch
Changes in V2:
https://lore.kernel.org/all/20230808074533.380537-1-anshuman.khandual@arm.com/
- s/treshhold/threshold
Changes in V1:
https://lore.kernel.org/all/20230804044720.1478900-1-anshuman.khandual@arm.com/
Anshuman Khandual (3):
coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus
coresight: etm: Make cycle count threshold user configurable
Documentation: coresight: Add cc_threshold tunable
Documentation/arch/arm64/silicon-errata.rst | 10 +++++
Documentation/trace/coresight/coresight.rst | 4 ++
.../hwtracing/coresight/coresight-etm-perf.c | 2 +
.../coresight/coresight-etm4x-core.c | 45 ++++++++++++++++++-
4 files changed, 59 insertions(+), 2 deletions(-)
--
2.25.1
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