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Message-ID: <cbdcf645-f473-f10c-a76e-feb6316d2a47@wanadoo.fr>
Date: Mon, 21 Aug 2023 07:40:26 +0200
From: Christophe JAILLET <christophe.jaillet@...adoo.fr>
To: Christophe Leroy <christophe.leroy@...roup.eu>,
Herve Codina <herve.codina@...tlin.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, Andrew Lunn <andrew@...n.ch>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Lee Jones <lee@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Qiang Zhao <qiang.zhao@....com>, Li Yang <leoyang.li@....com>,
Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>,
Jaroslav Kysela <perex@...ex.cz>,
Takashi Iwai <tiwai@...e.com>,
Shengjiu Wang <shengjiu.wang@...il.com>,
Xiubo Li <Xiubo.Lee@...il.com>,
Fabio Estevam <festevam@...il.com>,
Nicolin Chen <nicoleotsuka@...il.com>
Cc: netdev@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
alsa-devel@...a-project.org,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v4 20/28] wan: qmc_hdlc: Add runtime timeslots changes
support
Le 18/08/2023 à 18:39, Christophe Leroy a écrit :
> From: Herve Codina <herve.codina@...tlin.com>
>
> QMC channels support runtime timeslots changes but nothing is done at
> the QMC HDLC driver to handle these changes.
>
> Use existing IFACE ioctl in order to configure the timeslots to use.
>
> Signed-off-by: Herve Codina <herve.codina@...tlin.com>
> Reviewed-by: Christophe Leroy <christophe.leroy@...roup.eu>
> Signed-off-by: Christophe Leroy <christophe.leroy@...roup.eu>
> ---
Hi,
a few nits below, should there be a v5.
> drivers/net/wan/fsl_qmc_hdlc.c | 169 ++++++++++++++++++++++++++++++++-
> 1 file changed, 168 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/wan/fsl_qmc_hdlc.c b/drivers/net/wan/fsl_qmc_hdlc.c
> index 4f84ac5fc63e..4b8cb5761fd1 100644
> --- a/drivers/net/wan/fsl_qmc_hdlc.c
> +++ b/drivers/net/wan/fsl_qmc_hdlc.c
> @@ -32,6 +32,7 @@ struct qmc_hdlc {
> struct qmc_hdlc_desc tx_descs[8];
> unsigned int tx_out;
> struct qmc_hdlc_desc rx_descs[4];
> + u32 slot_map;
> };
>
> static inline struct qmc_hdlc *netdev_to_qmc_hdlc(struct net_device *netdev)
> @@ -202,6 +203,162 @@ static netdev_tx_t qmc_hdlc_xmit(struct sk_buff *skb, struct net_device *netdev)
> return NETDEV_TX_OK;
> }
>
> +static int qmc_hdlc_xlate_slot_map(struct qmc_hdlc *qmc_hdlc,
> + u32 slot_map, struct qmc_chan_ts_info *ts_info)
> +{
> + u64 ts_mask_avail;
> + unsigned int bit;
> + unsigned int i;
> + u64 ts_mask;
> + u64 map = 0;
This init looks useless.
> +
> + /* Tx and Rx masks must be identical */
> + if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
> + dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch (0x%llx, 0x%llx)\n",
> + ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
> + return -EINVAL;
> + }
> +
> + ts_mask_avail = ts_info->rx_ts_mask_avail;
> + ts_mask = 0;
> + map = slot_map;
> + bit = 0;
> + for (i = 0; i < 64; i++) {
> + if (ts_mask_avail & BIT_ULL(i)) {
> + if (map & BIT_ULL(bit))
> + ts_mask |= BIT_ULL(i);
> + bit++;
> + }
> + }
> +
> + if (hweight64(ts_mask) != hweight64(map)) {
> + dev_err(qmc_hdlc->dev, "Cannot translate timeslots 0x%llx -> (0x%llx,0x%llx)\n",
> + map, ts_mask_avail, ts_mask);
> + return -EINVAL;
> + }
> +
> + ts_info->tx_ts_mask = ts_mask;
> + ts_info->rx_ts_mask = ts_mask;
> + return 0;
> +}
> +
> +static int qmc_hdlc_xlate_ts_info(struct qmc_hdlc *qmc_hdlc,
> + const struct qmc_chan_ts_info *ts_info, u32 *slot_map)
> +{
> + u64 ts_mask_avail;
> + unsigned int bit;
> + unsigned int i;
> + u64 ts_mask;
> + u64 map = 0;
This init looks useless.
> +
> + /* Tx and Rx masks must be identical */
> + if (ts_info->rx_ts_mask_avail != ts_info->tx_ts_mask_avail) {
> + dev_err(qmc_hdlc->dev, "tx and rx available timeslots mismatch (0x%llx, 0x%llx)\n",
> + ts_info->rx_ts_mask_avail, ts_info->tx_ts_mask_avail);
> + return -EINVAL;
> + }
> + if (ts_info->rx_ts_mask != ts_info->tx_ts_mask) {
> + dev_err(qmc_hdlc->dev, "tx and rx timeslots mismatch (0x%llx, 0x%llx)\n",
> + ts_info->rx_ts_mask, ts_info->tx_ts_mask);
> + return -EINVAL;
> + }
> +
> + ts_mask_avail = ts_info->rx_ts_mask_avail;
> + ts_mask = ts_info->rx_ts_mask;
> + map = 0;
> + bit = 0;
> + for (i = 0; i < 64; i++) {
> + if (ts_mask_avail & BIT_ULL(i)) {
> + if (ts_mask & BIT_ULL(i))
> + map |= BIT_ULL(bit);
> + bit++;
> + }
> + }
> +
> + if (hweight64(ts_mask) != hweight64(map)) {
> + dev_err(qmc_hdlc->dev, "Cannot translate timeslots (0x%llx,0x%llx) -> 0x%llx\n",
> + ts_mask_avail, ts_mask, map);
> + return -EINVAL;
> + }
> +
> + if (map >= BIT_ULL(32)) {
> + dev_err(qmc_hdlc->dev, "Slot map out of 32bit (0x%llx,0x%llx) -> 0x%llx\n",
> + ts_mask_avail, ts_mask, map);
> + return -EINVAL;
> + }
> +
> + *slot_map = map;
> + return 0;
> +}
...
> +static int qmc_hdlc_ioctl(struct net_device *netdev, struct if_settings *ifs)
> +{
> + struct qmc_hdlc *qmc_hdlc = netdev_to_qmc_hdlc(netdev);
> + te1_settings te1;
> +
> + switch (ifs->type) {
> + case IF_GET_IFACE:
> + ifs->type = IF_IFACE_E1;
> + if (ifs->size < sizeof(te1)) {
> + if (!ifs->size)
> + return 0; /* only type requested */
> +
> + ifs->size = sizeof(te1); /* data size wanted */
> + return -ENOBUFS;
> + }
> +
> + memset(&te1, 0, sizeof(te1));
> +
> + /* Update slot_map */
> + te1.slot_map = qmc_hdlc->slot_map;
> +
> + if (copy_to_user(ifs->ifs_ifsu.te1, &te1, sizeof(te1)))
~~
Extra space.
> + return -EFAULT;
> + return 0;
> +
> + case IF_IFACE_E1:
> + case IF_IFACE_T1:
> + if (!capable(CAP_NET_ADMIN))
> + return -EPERM;
> +
> + if (netdev->flags & IFF_UP)
> + return -EBUSY;
> +
> + if (copy_from_user(&te1, ifs->ifs_ifsu.te1, sizeof(te1)))
> + return -EFAULT;
> +
> + return qmc_hdlc_set_iface(qmc_hdlc, ifs->type, &te1);
> +
> + default:
> + return hdlc_ioctl(netdev, ifs);
> + }
> +}
...
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