linux-kernel - RE: [PATCH net-next v3 1/2] net/ethernet/realtek: Add Realtek automotive PCIe driver code

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4db3248874d64418b63fdf5c5e8a0f79@realtek.com>
Date:   Mon, 21 Aug 2023 15:07:53 +0000
From:   Justin Lai <justinlai0215@...ltek.com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     "kuba@...nel.org" <kuba@...nel.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [PATCH net-next v3 1/2] net/ethernet/realtek: Add Realtek automotive PCIe driver code

> > Sorry, please allow me to explain again.
> > The RTL90xx Series supports I2C, MDC/MDIO and SPI slave to access the
> registers of Ethernet Switch Core and the external CPU could manage it via
> these pins.
> 
> I was wondering if you had mis-understood my question. The bus 'master' is
> the device which controls the bus. SPI and MDIO has one bus master, and there
> can be multiple clients on the bus. I2C in theory can have multiple bus masters
> on one bus, bit it is not done too often. Your switch is a client.
> 
> So my question was, are the bus masters also on PCIE enpoints within the chip.
> From an architecture standpoint, it would make sense they are, all you need is
> one 4x PCIE slot, and this chip gives you everything you need. But you can also
> make use of the SoCs I2C, SPI or MDIO bus.
> 
>     Andrew

Thanks, I understand what you mean.
But I2C, SPI, MDIO are connected to the SoC through this chip's external pins, not on the PCIe bus.
Actually, there is the other function in the PCIe GMAC(Multiple function) to manage the registers of Switch Core.
Should they be integrated into the MFD driver?
Not everyone will use this function.