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Message-Id: <20230822-tc358768-v3-0-c82405dac0c1@ideasonboard.com>
Date: Tue, 22 Aug 2023 19:19:33 +0300
From: Tomi Valkeinen <tomi.valkeinen@...asonboard.com>
To: Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>,
Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Péter Ujfalusi <peter.ujfalusi@...il.com>,
Maxim Schwalm <maxim.schwalm@...il.com>,
Francesco Dolcini <francesco@...cini.it>
Cc: dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Aradhya Bhatia <a-bhatia1@...com>,
Tomi Valkeinen <tomi.valkeinen@...asonboard.com>,
Thierry Reding <treding@...dia.com>,
Thierry Reding <thierry.reding@...il.com>
Subject: [PATCH v3 00/12] drm/bridge: tc358768: Fixes and timings
improvements
This series contains various fixes and cleanups for TC358768. The target
of this work is to get TC358768 working on Toradex's AM62 based board,
which has the following display pipeline:
AM62 DPI -> TC358768 -> LT8912B -> HDMI connector
The main thing the series does is to improve the DSI HSW, HFP and VSDly
calculations.
Tomi
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@...asonboard.com>
---
Changes in v3:
- Add Peter's reviewed-bys
- Move "Default to positive h/v syncs" earlier in the series to avoid
regression in the middle of the series
- Link to v2: https://lore.kernel.org/r/20230816-tc358768-v2-0-242b9d5f703a@ideasonboard.com
Changes in v2:
- Add "drm/tegra: rgb: Parameterize V- and H-sync polarities" so that
Tegra can configure the polarities correctly.
- Add "drm/bridge: tc358768: Default to positive h/v syncs" as we don't
(necessarily) have the polarities set in the mode.
- Drop "drm/bridge: tc358768: Add DRM_BRIDGE_ATTACH_NO_CONNECTOR
support" as it's not needed for DRM_BRIDGE_ATTACH_NO_CONNECTOR
support.
- Link to v1: https://lore.kernel.org/r/20230804-tc358768-v1-0-1afd44b7826b@ideasonboard.com
---
Thierry Reding (1):
drm/tegra: rgb: Parameterize V- and H-sync polarities
Tomi Valkeinen (11):
drm/bridge: tc358768: Fix use of uninitialized variable
drm/bridge: tc358768: Default to positive h/v syncs
drm/bridge: tc358768: Fix bit updates
drm/bridge: tc358768: Cleanup PLL calculations
drm/bridge: tc358768: Use struct videomode
drm/bridge: tc358768: Print logical values, not raw register values
drm/bridge: tc358768: Use dev for dbg prints, not priv->dev
drm/bridge: tc358768: Rename dsibclk to hsbyteclk
drm/bridge: tc358768: Clean up clock period code
drm/bridge: tc358768: Fix tc358768_ns_to_cnt()
drm/bridge: tc358768: Attempt to fix DSI horizontal timings
drivers/gpu/drm/bridge/tc358768.c | 381 ++++++++++++++++++++++++++++----------
drivers/gpu/drm/tegra/rgb.c | 16 +-
2 files changed, 295 insertions(+), 102 deletions(-)
---
base-commit: 25205087df1ffe06ccea9302944ed1f77dc68c6f
change-id: 20230804-tc358768-1b6949ef2e3d
Best regards,
--
Tomi Valkeinen <tomi.valkeinen@...asonboard.com>
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