linux-kernel - [PATCH] drm/amdgpu: Clean up errors in mxgpu

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Message-ID: <1c0204f7.623.18a21b13e92.Coremail.chenxuebing@jari.cn>
Date:   Wed, 23 Aug 2023 17:19:38 +0800 (GMT+08:00)
From:   "XueBing Chen" <chenxuebing@...i.cn>
To:     alexander.deucher@....com, airlied@...il.com, daniel@...ll.ch
Cc:     amd-gfx@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH] drm/amdgpu: Clean up errors in mxgpu_ai.c

Fix the following errors reported by checkpatch:

ERROR: open brace '{' following function definitions go on the next line
ERROR: space required before the open parenthesis '('
ERROR: space required before the open brace '{'
ERROR: trailing whitespace
ERROR: switch and case should be at the same indent

Signed-off-by: XueBing Chen <chenxuebing@...i.cn>
---
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 63725b2ebc03..9941c1f69658 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -75,7 +75,8 @@ static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev,
 	return 0;
 }
 
-static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) {
+static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev)
+{
 	return RREG8(AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE) & 2;
 }
 
@@ -117,7 +118,8 @@ static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event)
 }
 
 static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,
-	      enum idh_request req, u32 data1, u32 data2, u32 data3) {
+	      enum idh_request req, u32 data1, u32 data2, u32 data3)
+{
 	u32 reg;
 	int r;
 	uint8_t trn;
@@ -135,7 +137,7 @@ static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev,
 			pr_err("trn=%x ACK should not assert! wait again !\n", trn);
 			msleep(1);
 		}
-	} while(trn);
+	} while (trn);
 
 	reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
 					     mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0));
@@ -182,11 +184,11 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
 				RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0,
 					mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2));
 		}
-	} else if (req == IDH_REQ_GPU_INIT_DATA){
+	} else if (req == IDH_REQ_GPU_INIT_DATA) {
 		/* Dummy REQ_GPU_INIT_DATA handling */
 		r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY);
 		/* version set to 0 since dummy */
-		adev->virt.req_init_data_ver = 0;	
+		adev->virt.req_init_data_ver = 0;
 	}
 
 	return 0;
@@ -316,14 +318,14 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
 	enum idh_event event = xgpu_ai_mailbox_peek_msg(adev);
 
 	switch (event) {
-		case IDH_FLR_NOTIFICATION:
+	case IDH_FLR_NOTIFICATION:
 		if (amdgpu_sriov_runtime(adev) && !amdgpu_in_reset(adev))
 			WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain,
 								&adev->virt.flr_work),
 				  "Failed to queue work! at %s",
 				  __func__);
 		break;
-		case IDH_QUERY_ALIVE:
+	case IDH_QUERY_ALIVE:
 			xgpu_ai_mailbox_send_ack(adev);
 			break;
 		/* READY_TO_ACCESS_GPU is fetched by kernel polling, IRQ can ignore
@@ -333,7 +335,7 @@ static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev,
 		case IDH_CLR_MSG_BUF:
 		case IDH_FLR_NOTIFICATION_CMPL:
 		case IDH_READY_TO_ACCESS_GPU:
-		default:
+	default:
 		break;
 	}
 
-- 
2.17.1