Date:   Wed, 23 Aug 2023 12:49:20 +0100
From:   Andre Przywara <andre.przywara@....com>
To:     Александр Шубин 
        <privatesub2@...il.com>
Cc:     linux-kernel@...r.kernel.org,
        Thierry Reding <thierry.reding@...il.com>,
        Uwe Kleine-König <u.kleine-koenig@...gutronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        Samuel Holland <samuel@...lland.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Cristian Ciocaltea <cristian.ciocaltea@...labora.com>,
        linux-pwm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
        linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v5 1/3] dt-bindings: pwm: Add binding for Allwinner
 D1/T113-S3/R329 PWM controller

Hi,

On 23/08/2023 07:57, Александр Шубин wrote:
> Hi Andre,
> 
> вт, 22 авг. 2023 г. в 12:49, Andre Przywara <andre.przywara@....com>:
>>
>> On Mon, 14 Aug 2023 16:32:16 +0300
>> Aleksandr Shubin <privatesub2@...il.com> wrote:
>>
>> Hi Aleksandr,
>>
>>> Allwinner's D1, T113-S3 and R329 SoCs have a new pwm
>>> controller witch is different from the previous pwm-sun4i.
>>>
>>> The D1 and T113 are identical in terms of peripherals,
>>> they differ only in the architecture of the CPU core, and
>>> even share the majority of their DT. Because of that,
>>> using the same compatible makes sense.
>>> The R329 is a different SoC though, and should have
>>> a different compatible string added, especially as there
>>> is a difference in the number of channels.
>>>
>>> D1 and T113s SoCs have one PWM controller with 8 channels.
>>> R329 SoC has two PWM controllers in both power domains, one of
>>> them has 9 channels (CPUX one) and the other has 6 (CPUS one).
>>>
>>> Add a device tree binding for them.
>>>
>>> Signed-off-by: Aleksandr Shubin <privatesub2@...il.com>
>>> ---
>>>   .../bindings/pwm/allwinner,sun20i-pwm.yaml    | 85 +++++++++++++++++++
>>>   1 file changed, 85 insertions(+)
>>>   create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
>>> new file mode 100644
>>> index 000000000000..9512d4bed322
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
>>> @@ -0,0 +1,85 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Allwinner D1, T113-S3 and R329 PWM
>>> +
>>> +maintainers:
>>> +  - Aleksandr Shubin <privatesub2@...il.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    oneOf:
>>> +      - const: allwinner,sun20i-d1-pwm
>>> +      - items:
>>> +          - const: allwinner,sun20i-r329-pwm
>>> +          - const: allwinner,sun20i-d1-pwm
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  "#pwm-cells":
>>> +    const: 3
>>> +
>>> +  clocks:
>>> +    items:
>>> +      - description: 24 MHz oscillator
>>> +      - description: Bus Clock
>>
>> The manual tells me that the new PWMs can also use APB0 as the
>> input clock, which (finally!) allows PWM frequencies above 24 MHz.
>> So we should have an explicit reference to that clock - even if the bus
>> clock happens to be gated version of APB0.
> 
> Should I change it to something like this:
>      pwm: pwm@...0c00 {
>        compatible = "allwinner,sun20i-d1-pwm";
>        reg = <0x02000c00 0x400>;
>        clocks = <&ccu CLK_BUS_PWM>, <&dcxo>, <&ccu CLK_APB0>;
>        clock-names = "bus", "hosc", "apb0";
>        resets = <&ccu RST_BUS_PWM>;
>        #pwm-cells = <0x3>;
>      };

Yes, that is what I had in mind!
It shouldn't be too hard to add support for this in the driver as well.

Thanks!
Andre

> 
>>
>> Cheers,
>> Andre
>>
>>> +
>>> +  clock-names:
>>> +    items:
>>> +      - const: hosc
>>> +      - const: bus
>>> +
>>> +  resets:
>>> +    maxItems: 1
>>> +
>>> +  allwinner,pwm-channels:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    description: The number of PWM channels configured for this instance
>>> +    enum: [6, 9]
>>> +
>>> +allOf:
>>> +  - $ref: pwm.yaml#
>>> +
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            const: allwinner,sun20i-r329-pwm
>>> +
>>> +    then:
>>> +      required:
>>> +        - allwinner,pwm-channels
>>> +
>>> +    else:
>>> +      properties:
>>> +        allwinner,pwm-channels: false
>>> +
>>> +unevaluatedProperties: false
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - "#pwm-cells"
>>> +  - clocks
>>> +  - clock-names
>>> +  - resets
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/clock/sun20i-d1-ccu.h>
>>> +    #include <dt-bindings/reset/sun20i-d1-ccu.h>
>>> +
>>> +    pwm: pwm@...0c00 {
>>> +      compatible = "allwinner,sun20i-d1-pwm";
>>> +      reg = <0x02000c00 0x400>;
>>> +      clocks = <&dcxo>, <&ccu CLK_BUS_PWM>;
>>> +      clock-names = "hosc", "bus";
>>> +      resets = <&ccu RST_BUS_PWM>;
>>> +      #pwm-cells = <0x3>;
>>> +    };
>>> +
>>> +...
>>
> 
> Cheers,
> Aleksandr
> 

Powered by blists - more mailing lists