linux-kernel - Re: [PATCH v3 08/10] x86/hyperv: Use TDX GHCI to access some MSRs in a TDX VM with the paravisor

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Message-ID: <4ae6b858-da04-3f7f-dfd9-cd4c03716314@gmail.com>
Date:   Thu, 24 Aug 2023 22:44:23 +0800
From:   Tianyu Lan <ltykernel@...il.com>
To:     Dexuan Cui <decui@...rosoft.com>, ak@...ux.intel.com,
        arnd@...db.de, bp@...en8.de, brijesh.singh@....com,
        dan.j.williams@...el.com, dave.hansen@...el.com,
        dave.hansen@...ux.intel.com, haiyangz@...rosoft.com, hpa@...or.com,
        jane.chu@...cle.com, kirill.shutemov@...ux.intel.com,
        kys@...rosoft.com, linux-hyperv@...r.kernel.org, luto@...nel.org,
        mingo@...hat.com, peterz@...radead.org, rostedt@...dmis.org,
        sathyanarayanan.kuppuswamy@...ux.intel.com, seanjc@...gle.com,
        tglx@...utronix.de, tony.luck@...el.com, wei.liu@...nel.org,
        Jason@...c4.com, nik.borisov@...e.com, mikelley@...rosoft.com
Cc:     x86@...nel.org, linux-kernel@...r.kernel.org,
        linux-arch@...r.kernel.org, Tianyu.Lan@...rosoft.com,
        rick.p.edgecombe@...el.com, andavis@...hat.com, mheslin@...hat.com,
        vkuznets@...hat.com, xiaoyao.li@...el.com
Subject: Re: [PATCH v3 08/10] x86/hyperv: Use TDX GHCI to access some MSRs in
 a TDX VM with the paravisor

On 8/24/2023 4:07 PM, Dexuan Cui wrote:
> When the paravisor is present, a SNP VM must use GHCB to access some
> special MSRs, including HV_X64_MSR_GUEST_OS_ID and some SynIC MSRs.
> 
> Similarly, when the paravisor is present, a TDX VM must use TDX GHCI
> to access the same MSRs.
> 
> Implement hv_tdx_msr_write() and hv_tdx_msr_read(), and use the helper
> functions hv_ivm_msr_read() and hv_ivm_msr_write() to access the MSRs
> in a unified way for SNP/TDX VMs with the paravisor.
> 
> Do not export hv_tdx_msr_write() and hv_tdx_msr_read(), because we never
> really used hv_ghcb_msr_write() and hv_ghcb_msr_read() in any module.
> 
> Update arch/x86/include/asm/mshyperv.h so that the kernel can still build
> if CONFIG_AMD_MEM_ENCRYPT or CONFIG_INTEL_TDX_GUEST is not set, or
> neither is set.
> 
> Signed-off-by: Dexuan Cui <decui@...rosoft.com>

Reviewed-by: Tianyu Lan <tiala@...rosoft.com>