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Message-Id: <20230825-pll-mipi_keep_rate-v1-2-35bc43570730@oltmanns.dev>
Date: Fri, 25 Aug 2023 07:36:38 +0200
From: Frank Oltmanns <frank@...manns.dev>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Maxime Ripard <mripard@...nel.org>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>, Ondrej Jirman <x@...x.eu>,
Icenowy Zheng <uwu@...nowy.me>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
dri-devel@...ts.freedesktop.org,
Frank Oltmanns <frank@...manns.dev>
Subject: [PATCH 2/3] clk: sunxi-ng: a64: keep rate of pll-mipi stable
across parent rate changes
Keep the clock rate of Allwinner A64's pll-mipi even when the parent
(pll-video0) changes its rate. This is required, to drive both an LCD
and HDMI display, because both have pll-video0 as an ancestor.
Signed-off-by: Frank Oltmanns <frank@...manns.dev>
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 8951ffc14ff5..d22094ce1d66 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -180,7 +180,8 @@ static struct ccu_nkm pll_mipi_clk = {
.reg = 0x040,
.hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
&ccu_nkm_ops,
- CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT),
+ CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT |
+ CLK_KEEP_RATE),
.features = CCU_FEATURE_CLOSEST_RATE,
},
};
--
2.41.0
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