[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20230825081328.204442-5-william.qiu@starfivetech.com>
Date: Fri, 25 Aug 2023 16:13:28 +0800
From: William Qiu <william.qiu@...rfivetech.com>
To: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-pwm@...r.kernel.org>
CC: Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh+dt@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
"Paul Walmsley" <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Hal Feng <hal.feng@...rfivetech.com>,
William Qiu <william.qiu@...rfivetech.com>
Subject: [RFC v4 4/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration
Add StarFive JH7100 PWM controller node and add PWM pins configuration
on VisionFive 2 board.
Signed-off-by: William Qiu <william.qiu@...rfivetech.com>
---
.../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++
2 files changed, 33 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
index b93ce351a90f..746867b882b0 100644
--- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
@@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN,
};
};
+ pwm_pins: pwm-0 {
+ pwm-pins {
+ pinmux = <GPIOMUX(7,
+ GPO_PWM_PAD_OUT_BIT0,
+ GPO_PWM_PAD_OE_N_BIT0,
+ GPI_NONE)>,
+ <GPIOMUX(5,
+ GPO_PWM_PAD_OUT_BIT1,
+ GPO_PWM_PAD_OE_N_BIT1,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <35>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
uart3_pins: uart3-0 {
rx-pins {
pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
@@ -154,6 +172,12 @@ &osc_aud {
clock-frequency = <27000000>;
};
+&ptc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 4218621ea3b9..7f5bb19e636e 100644
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -248,5 +248,14 @@ watchdog@...80000 {
resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
<&rstgen JH7100_RSTN_WDT>;
};
+
+ ptc: pwm@...90000 {
+ compatible = "starfive,jh7100-pwm";
+ reg = <0x0 0x12490000 0x0 0x10000>;
+ clocks = <&clkgen JH7100_CLK_PWM_APB>;
+ resets = <&rstgen JH7100_RSTN_PWM_APB>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
};
};
--
2.34.1
Powered by blists - more mailing lists