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Message-ID: <20230826-reverse-unroll-a2e0b2365dc1@spud>
Date: Sat, 26 Aug 2023 10:28:40 +0100
From: Conor Dooley <conor@...nel.org>
To: Inochi Amaoto <inochiama@...look.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Chen-Yu Tsai <wens@...e.org>,
Jernej Skrabec <jernej.skrabec@...il.com>,
Samuel Holland <samuel@...lland.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Heiko Stuebner <heiko@...ech.de>, Wei Fu <wefu@...hat.com>,
Guo Ren <guoren@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-sunxi@...ts.linux.dev,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: dts: allwinner: d1: Add PMU event node
On Sat, Aug 26, 2023 at 04:38:53PM +0800, Inochi Amaoto wrote:
> D1 has several pmu events supported by opensbi.
> These events can be used by perf for profiling.
>
> Signed-off-by: Inochi Amaoto <inochiama@...look.com>
Could you please include a link to some documentation as to where these
values came from? I know several people have had some trouble with
understanding the pmu DT stuff & having some documentation would make
this an in-tree end-to-end example.
Thanks,
Conor.
> ---
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> index 8275630af977..d9031ccdec89 100644
> --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> @@ -72,5 +72,45 @@ plic: interrupt-controller@...00000 {
> #address-cells = <0>;
> #interrupt-cells = <2>;
> };
> +
> + pmu {
> + compatible = "riscv,pmu";
> + riscv,event-to-mhpmcounters =
> + <0x00003 0x00003 0x00000008>,
> + <0x00004 0x00004 0x00000010>,
> + <0x00005 0x00005 0x00000200>,
> + <0x00006 0x00006 0x00000100>,
> + <0x10000 0x10000 0x00004000>,
> + <0x10001 0x10001 0x00008000>,
> + <0x10002 0x10002 0x00010000>,
> + <0x10003 0x10003 0x00020000>,
> + <0x10019 0x10019 0x00000040>,
> + <0x10021 0x10021 0x00000020>;
> + riscv,event-to-mhpmevent =
> + <0x00003 0x00000000 0x00000001>,
> + <0x00004 0x00000000 0x00000002>,
> + <0x00005 0x00000000 0x00000007>,
> + <0x00006 0x00000000 0x00000006>,
> + <0x0000a 0x00000000 0x0000000b>,
> + <0x10000 0x00000000 0x0000000c>,
> + <0x10001 0x00000000 0x0000000d>,
> + <0x10002 0x00000000 0x0000000e>,
> + <0x10003 0x00000000 0x0000000f>,
> + <0x10019 0x00000000 0x00000004>,
> + <0x10021 0x00000000 0x00000003>;
> + riscv,raw-event-to-mhpmcounters =
> + <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
> + <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
> + <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
> + <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
> + <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
> + <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
> + <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
> + <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
> + <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
> + <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
> + <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
> + <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
> + };
> };
> };
> --
> 2.41.0
>
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