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Message-ID: <20230826-copper-suffocate-5f4f0e67f9a7@spud>
Date:   Sat, 26 Aug 2023 10:56:29 +0100
From:   Conor Dooley <conor@...nel.org>
To:     Evan Green <evan@...osinc.com>
Cc:     Palmer Dabbelt <palmer@...osinc.com>,
        Anup Patel <apatel@...tanamicro.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Heiko Stuebner <heiko@...ech.de>,
        Jonathan Corbet <corbet@....net>, linux-doc@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Conor Dooley <conor.dooley@...rochip.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Bagas Sanjaya <bagasdotme@...il.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-riscv@...ts.infradead.org,
        Andrew Jones <ajones@...tanamicro.com>
Subject: Re: [PATCH v5] RISC-V: Show accurate per-hart isa in /proc/cpuinfo

On Sat, Aug 26, 2023 at 12:26:25AM +0100, Conor Dooley wrote:
> On Fri, Aug 25, 2023 at 04:11:38PM -0700, Evan Green wrote:
> > In /proc/cpuinfo, most of the information we show for each processor is
> > specific to that hart: marchid, mvendorid, mimpid, processor, hart,
> > compatible, and the mmu size. But the ISA string gets filtered through a
> > lowest common denominator mask, so that if one CPU is missing an ISA
> > extension, no CPUs will show it.
> > 
> > Now that we track the ISA extensions for each hart, let's report ISA
> > extension info accurately per-hart in /proc/cpuinfo. We cannot change
> > the "isa:" line, as usermode may be relying on that line to show only
> > the common set of extensions supported across all harts. Add a new "hart
> > isa" line instead, which reports the true set of extensions for that
> > hart.
> > 
> > Signed-off-by: Evan Green <evan@...osinc.com>
> > Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
> 
> > Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
> 
> Can you drop this if you repost?
> 
> > +"isa" vs "hart isa" lines in /proc/cpuinfo
> > +------------------------------------------
> > +
> > +The "isa" line in /proc/cpuinfo describes the lowest common denominator of
> > +RISC-V ISA extensions recognized by the kernel and implemented on all harts. The
> > +"hart isa" line, in contrast, describes the set of extensions recognized by the
> > +kernel on the particular hart being described, even if those extensions may not
> > +be present on all harts in the system.
> 
> > In both cases, the presence of a feature
> > +in these lines guarantees only that the hardware has the described capability.
> > +Additional kernel support or policy control changes may be required before a
> > +feature is fully usable by userspace programs.
> 
> I do not think that "in both cases" matches the expectations of
> userspace for the existing line. It's too late at night for me to think
> properly, but I think our existing implementation does work like you
> have documented for FD/V. I think I previously mentioned that it could
> misreport things for vector during the review of the vector series but
> forgot about it until now.

I went and checked, and yes it does currently do that for vector. I
don't think that that is what userspace would expect, that Google
cpu_features project for example would draw incorrect conclusions.

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