linux-kernel - Re: Synopsys XGMII MAC and USXGMII interfaces

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Message-ID: <q325fnweuebsmjrsfi3xfnttetgjmjsssvlscgq6lftg6acjsh@zkku2kmtpbmk>
Date:   Sun, 27 Aug 2023 04:05:26 +0300
From:   Serge Semin <fancer.lancer@...il.com>
To:     "Russell King (Oracle)" <linux@...linux.org.uk>
Cc:     Jakub Kicinski <kuba@...nel.org>,
        Rohan G Thomas <rohan.g.thomas@...el.com>,
        "David S . Miller" <davem@...emloft.net>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Jose Abreu <joabreu@...opsys.com>,
        Eric Dumazet <edumazet@...gle.com>,
        Paolo Abeni <pabeni@...hat.com>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Giuseppe Cavallaro <peppe.cavallaro@...com>,
        netdev@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Conor Dooley <conor.dooley@...rochip.com>
Subject: Re: Synopsys XGMII MAC and USXGMII interfaces

On Wed, Aug 23, 2023 at 11:58:32AM +0100, Russell King (Oracle) wrote:
> Part 2 of the discussion...
> 
> A similar issue applies to PHY_INTERFACE_MODE_USXGMII, but is reversed.
> USXGMII supports 10M, 100M, 1G, 2.5G, 5G and 10G. Phylink allows all of
> these because that's what the appropriate standard says. dwxgmac2
> initialises config register settings for speeds from 10M up to 10G.
> However, the PHY_INTERFACE_MODE_USXGMII switch() block in
> stmmac_mac_link_up() only handles 2.5G, 5G and 10G. Shouldn't it handle
> the other speed cases - it looks like the MAC does support them.

AFAICS yes, it should.

> 
> The initialisation done by dwxgmac2_setup() does setup control register
> masks for everything from 10M to 10G, so on the face of it, it looks
> like a mistake in stmmac_mac_link_up().

Right.

> 
> If it's something outside of the MAC that doesn't support these speeds
> when operating as USXGMII, then that needs to be handled.

Based on what USXGMII is mentioned on just a single Synopsys PCS/PHY
page on the Synopsys site I guess that DW XGMAC doesn't know anything
about the USXGMII interface. As I explained in my comment to part 1 it
just exposes a multi-protocol port(s) capable of working as XGMII,
GMII or MII. Then XPCS consumes/supplies the data from/to the
activated interface and performs a respective data encoding/decoding.
On the lowest level DW PMA/PHY does the serdes-ing. See the brief
description on the Synopsys 10G PHY page (on the "Downloads and
Documentation" menu):
https://www.synopsys.com/dw/ipdir.php?ds=dwc_multi_protocol_10g_phy
it has two layers:
- Multi-protocol PCS
- Multi-protocol PHY
both are designed to provide USXGMII and SGMII interfaces. 

> 
> The other weird thing is that when using PHY_INTERFACE_MODE_USXGMII
> with XPCS, XPCS supports 1G, 2.5G and 10G ethtool link modes, but not
> 5G. So combining the implementation in stmmac_mac_link_up(), that
> means only 2.5G and 10G can actually be functional. Is that a fair
> assessment of the USXGMII situation with stmmac?

AFAICS assessment seems quite fair. If USXGMII is an external
interface then these ethtool link modes are just irrelevant. Despite
of the XLGMII case I don't just see of how USXGMII mode could be used
as an internal MAC-PCS. Since it's an external interface then the
actual link modes are supposed to be retrieved from an external PHY.
Seeing STMMAC driver doesn't support an external PHY attached if XPCS
performs C73 auto-negotiation, then the xpcs_usxgmii_features array
should have been filled with all the USXGMII-speed-compatible link
modes.

-Serge(y)

> 
> Thanks.
> 
> -- 
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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