linux-kernel - Re: [PATCH v6 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO documentation

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Message-ID: <c984d558-11b5-d5ea-9819-7641129de584@linaro.org>
Date:   Mon, 28 Aug 2023 12:36:58 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Tomer Maimon <tmaimon77@...il.com>
Cc:     linus.walleij@...aro.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        avifishman70@...il.com, tali.perry1@...il.com, joel@....id.au,
        venture@...gle.com, yuenn@...gle.com, benjaminfair@...gle.com,
        j.neuschaefer@....net, openbmc@...ts.ozlabs.org,
        linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v6 1/2] dt-binding: pinctrl: Add NPCM8XX pinctrl and GPIO
 documentation

On 28/08/2023 12:26, Tomer Maimon wrote:
> Hi Krzysztof,
> 
> Thanks for your comments
> 
> On Mon, 28 Aug 2023 at 10:10, Krzysztof Kozlowski
> <krzysztof.kozlowski@...aro.org> wrote:
>>
>> On 27/08/2023 22:36, Tomer Maimon wrote:
>>> Added device tree binding documentation for Nuvoton Arbel BMC NPCM8XX
>>> pinmux and GPIO controller.
>>>
>>> Signed-off-by: Tomer Maimon <tmaimon77@...il.com>
>>> Reviewed-by: Rob Herring <robh@...nel.org>
>>> ---
>>
>>
>>> +  '^pin':
>>> +    $ref: pincfg-node.yaml#
>>> +
>>> +    properties:
>>> +      pins:
>>> +        description:
>>> +          A list of pins to configure in certain ways, such as enabling
>>> +          debouncing
>>
>> What pin names are allowed?
> Do you mean to describe all the allowed pin items?
> for example:
>       items:
>         pattern:
> 'GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA|GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL'
> or
>       items:
>         pattern: '^GPIO([0-9]|[0-9][0-9]|[1-2][0-4][0-9]|25[0-6])$'
> 
> is good enough?

Something like this. Whichever is correct.

>>
>>> +
>>> +      bias-disable: true
>>> +

>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +    #include <dt-bindings/gpio/gpio.h>
>>> +
>>> +    soc {
>>> +      #address-cells = <2>;
>>> +      #size-cells = <2>;
>>> +
>>> +      pinctrl: pinctrl@...00260 {
>>
>> Nothing improved here. Test your DTS. This is being reported - I checked.
> what do you suggest since the pinctrl doesn't have a reg parameter,
> maybe pinctrl: pinctrl@0?

It has ranges, so yes @0 looks correct here. Which leds to second
question - how pinctrl could have @0? It's already taken by SoC! So your
DTS here - unit address and ranges - are clearly wrong.


> BTW, I have run both dt_binding_check and W=1 dtbs_check, and didn't
> see an issue related to the pinctrl: pinctrl@...00260, do I need to
> add another flag to see the issue?

Did you read my message last time? I said - it's about DTS, not the binding.



Best regards,
Krzysztof