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Message-ID: <20230828171910.GB14596@pendragon.ideasonboard.com>
Date: Mon, 28 Aug 2023 20:19:10 +0300
From: Laurent Pinchart <laurent.pinchart@...asonboard.com>
To: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Cc: rfoss@...nel.org, todor.too@...il.com, agross@...nel.org,
andersson@...nel.org, konrad.dybcio@...aro.org, mchehab@...nel.org,
hverkuil-cisco@...all.nl, sakari.ailus@...ux.intel.com,
andrey.konovalov@...aro.org, linux-media@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
stable@...r.kernel.org
Subject: Re: [PATCH v2 7/9] media: qcom: camss: Fix invalid clock enable bit
disjunction
Hi Bryan,
Thank you for the patch.
On Tue, Aug 22, 2023 at 09:06:24PM +0100, Bryan O'Donoghue wrote:
> define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)
>
> disjunction for gen2 ? BIT(7) : is a nop we are setting the same bit
> either way.
>
> Fixes: 4abb21309fda ("media: camss: csiphy: Move to hardcode CSI Clock Lane number")
> Cc: stable@...r.kernel.org
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@...asonboard.com>
> ---
> drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> index 04baa80494c66..4dba61b8d3f2a 100644
> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
> @@ -476,7 +476,7 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
>
> settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>
> - val = is_gen2 ? BIT(7) : CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
> for (i = 0; i < c->num_data; i++)
> val |= BIT(c->data[i].pos * 2);
>
> --
> 2.41.0
>
--
Regards,
Laurent Pinchart
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