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Message-ID: <20230828172705.GD14596@pendragon.ideasonboard.com>
Date:   Mon, 28 Aug 2023 20:27:05 +0300
From:   Laurent Pinchart <laurent.pinchart@...asonboard.com>
To:     Bryan O'Donoghue <bryan.odonoghue@...aro.org>
Cc:     rfoss@...nel.org, todor.too@...il.com, agross@...nel.org,
        andersson@...nel.org, konrad.dybcio@...aro.org, mchehab@...nel.org,
        hverkuil-cisco@...all.nl, sakari.ailus@...ux.intel.com,
        andrey.konovalov@...aro.org, linux-media@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        stable@...r.kernel.org
Subject: Re: [PATCH v2 9/9] media: qcom: camss: Fix csid-gen2 for test
 pattern generator

Hi Bryan,

Thank you for the patch.

On Tue, Aug 22, 2023 at 09:06:26PM +0100, Bryan O'Donoghue wrote:
> From: Andrey Konovalov <andrey.konovalov@...aro.org>
> 
> In the current driver csid Test Pattern Generator (TPG) doesn't work.
> This change:
> - fixes writing frame width and height values into CSID_TPG_DT_n_CFG_0
> - fixes the shift by one between test_pattern control value and the
>   actual pattern.
> - drops fixed VC of 0x0a which testing showed prohibited some test
>   patterns in the CSID to produce output.
> So that TPG starts working, but with the below limitations:
> - only test_pattern=9 works as it should
> - test_pattern=8 and test_pattern=7 produce black frame (all zeroes)
> - the rest of test_pattern's don't work (yavta doesn't get the data)
> - regardless of the CFA pattern set by 'media-ctl -V' the actual pixel
>   order is always the same (RGGB for any RAW8 or RAW10P format in
>   4608x2592 resolution).
> 
> Tested with:
> 
> RAW10P format, VC0:
>  media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4608x2592 field:none]'
>  media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4608x2592 field:none]'
>  media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
>  v4l2-ctl -d /dev/v4l-subdev6 -c test_pattern=9
>  yavta -B capture-mplane --capture=3 -n 3 -f SRGGB10P -s 4608x2592 /dev/video0
> 
> RAW10P format, VC1:
>  media-ctl -V '"msm_csid0":2[fmt:SRGGB10/4608x2592 field:none]'
>  media-ctl -V '"msm_vfe0_rdi1":0[fmt:SRGGB10/4608x2592 field:none]'
>  media-ctl -l '"msm_csid0":2->"msm_vfe0_rdi1":0[1]'
>  v4l2-ctl -d /dev/v4l-subdev6 -c test_pattern=9
>  yavta -B capture-mplane --capture=3 -n 3 -f SRGGB10P -s 4608x2592 /dev/video1
> 
> RAW8 format, VC0:
>  media-ctl --reset
>  media-ctl -V '"msm_csid0":0[fmt:SRGGB8/4608x2592 field:none]'
>  media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB8/4608x2592 field:none]'
>  media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
>  yavta -B capture-mplane --capture=3 -n 3 -f SRGGB8 -s 4608x2592 /dev/video0
> 
> Fixes: eebe6d00e9bf ("media: camss: Add support for CSID hardware version Titan 170")
> Cc: stable@...r.kernel.org
> Signed-off-by: Andrey Konovalov <andrey.konovalov@...aro.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>

Reviewed-by: Laurent Pinchart <laurent.pinchart@...asonboard.com>

> ---
>  drivers/media/platform/qcom/camss/camss-csid-gen2.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen2.c b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
> index 140c584bfb8b1..6ba2b10326444 100644
> --- a/drivers/media/platform/qcom/camss/camss-csid-gen2.c
> +++ b/drivers/media/platform/qcom/camss/camss-csid-gen2.c
> @@ -355,9 +355,6 @@ static void __csid_configure_stream(struct csid_device *csid, u8 enable, u8 vc)
>  		u8 dt_id = vc;
>  
>  		if (tg->enabled) {
> -			/* Config Test Generator */
> -			vc = 0xa;
> -
>  			/* configure one DT, infinite frames */
>  			val = vc << TPG_VC_CFG0_VC_NUM;
>  			val |= INTELEAVING_MODE_ONE_SHOT << TPG_VC_CFG0_LINE_INTERLEAVING_MODE;
> @@ -370,14 +367,14 @@ static void __csid_configure_stream(struct csid_device *csid, u8 enable, u8 vc)
>  
>  			writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED);
>  
> -			val = input_format->height & 0x1fff << TPG_DT_n_CFG_0_FRAME_HEIGHT;
> -			val |= input_format->width & 0x1fff << TPG_DT_n_CFG_0_FRAME_WIDTH;
> +			val = (input_format->height & 0x1fff) << TPG_DT_n_CFG_0_FRAME_HEIGHT;
> +			val |= (input_format->width & 0x1fff) << TPG_DT_n_CFG_0_FRAME_WIDTH;
>  			writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));
>  
>  			val = format->data_type << TPG_DT_n_CFG_1_DATA_TYPE;
>  			writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));
>  
> -			val = tg->mode << TPG_DT_n_CFG_2_PAYLOAD_MODE;
> +			val = (tg->mode - 1) << TPG_DT_n_CFG_2_PAYLOAD_MODE;
>  			val |= 0xBE << TPG_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD;
>  			val |= format->decode_format << TPG_DT_n_CFG_2_ENCODE_FORMAT;
>  			writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));

-- 
Regards,

Laurent Pinchart

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