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Message-ID: <dc2f32d3-001c-746f-6dc5-58a2a6a4a8e6@linaro.org>
Date: Tue, 29 Aug 2023 19:40:47 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Alex Bee <knaerzche@...il.com>, Heiko Stuebner <heiko@...ech.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>, Lee Jones <lee@...nel.org>,
Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>
Cc: Elaine Zhang <zhangqing@...k-chips.com>,
Johan Jonker <jbx6244@...il.com>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org, alsa-devel@...a-project.org,
linux-clk@...r.kernel.org, linux-phy@...ts.infradead.org,
Finley Xiao <finley.xiao@...k-chips.com>
Subject: Re: [PATCH 05/31] clk: rockchip: rk3128: Fix aclk_peri_src parent
On 29/08/2023 19:16, Alex Bee wrote:
> From: Finley Xiao <finley.xiao@...k-chips.com>
>
> According to the TRM there are no specific cpll_peri, gpll_div2_peri or
> gpll_div3_peri gates, but a single clk_peri_src gate and the peri mux
> directly connects to the plls respectivly the pll divider clocks.
> Fix this by creating a single gated composite.
>
> Also rename all occurrences of "aclk_peri_src*" to clk_peri_src, since it
> is the parent for both peri aclks and hclks and that also matches the
> naming in the TRM.
>
> Fixes: f6022e88faca ("clk: rockchip: add clock controller for rk3128")
> Signed-off-by: Finley Xiao <finley.xiao@...k-chips.com>
> [renamed aclk_peri_src -> clk_peri_src and added commit message]
> Signed-off-by: Alex Bee <knaerzche@...il.com>
Please send fixes as separate patchset. Don't mix it with other work and
definitely it should not be in the middle of the patchset.
Best regards,
Krzysztof
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