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Message-Id: <1693291534-32092-2-git-send-email-hongxing.zhu@nxp.com>
Date: Tue, 29 Aug 2023 14:45:32 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: vkoul@...nel.org, kishon@...nel.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
shawnguo@...nel.org, s.hauer@...gutronix.de, festevam@...il.com,
l.stach@...gutronix.de, a.fatoum@...gutronix.de,
u.kleine-koenig@...gutronix.de
Cc: hongxing.zhu@....com, linux-phy@...ts.infradead.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, kernel@...gutronix.de,
linux-imx@....com
Subject: [PATCH v1 1/3] dt-bindings: phy: Add i.MX8QM PCIe PHY binding
Add i.MX8QM PCIe PHY binding.
i.MX8QM HSIO(High Speed IO) module has three instances of single lane
SERDES PHYs, an instance of two lanes PCIe GEN3 controller, an
instance of single lane PCIe GEN3 controller, as well as an instance
of SATA 3.0 controller.
The HSIO module can be configured as the following different usecases.
1 - A two lanes PCIea and a single lane SATA.
2 - A single lane PCIea, a single lane PCIeb and a single lane SATA.
3 - A two lanes PCIea, a single lane PCIeb.
Signed-off-by: Richard Zhu <hongxing.zhu@....com>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 70 ++++++++++++++++++-
1 file changed, 67 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index 182a219387b0..764790f2b10b 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -17,16 +17,18 @@ properties:
enum:
- fsl,imx8mm-pcie-phy
- fsl,imx8mp-pcie-phy
+ - fsl,imx8qm-pcie-phy
reg:
maxItems: 1
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 5
clock-names:
- items:
- - const: ref
+ minItems: 1
+ maxItems: 5
resets:
minItems: 1
@@ -70,6 +72,36 @@ properties:
description: PCIe PHY power domain (optional).
maxItems: 1
+ hsio-cfg:
+ description: |
+ Specifies the different usecases supported by the HSIO(High Speed IO)
+ module. PCIEAX2SATA means two lanes PCIea and a single lane SATA.
+ PCIEAX1PCIEBX1SATA represents a single lane PCIea, a single lane
+ PCIeb and a single lane SATA. PCIEAX2PCIEBX1 on behalf of a two
+ lanes PCIea, a single lane PCIeb.
+ Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants to
+ be used (optional).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 3 ]
+
+ ctrl-csr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the ctrl-csr region containing the HSIO control and
+ status registers for PCIe or SATA controller (optional).
+
+ misc-csr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the misc-csr region containing the HSIO control and
+ status registers for misc (optional).
+
+ phy-csr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the phy-csr region containing the HSIO control and
+ status registers for phy (optional).
+
required:
- "#phy-cells"
- compatible
@@ -78,6 +110,38 @@ required:
- clock-names
- fsl,refclk-pad-mode
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx8qm-pcie-phy
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 5
+ clock-names:
+ oneOf:
+ - items:
+ - const: pipe_pclk
+ - const: ctrl_ips_clk
+ - const: phy_ips_clk
+ - const: misc_ips_clk
+ - items:
+ - const: apb_pclk
+ - const: pipe_pclk
+ - const: ctrl_ips_clk
+ - const: phy_ips_clk
+ - const: misc_ips_clk
+ else:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names:
+ items:
+ - const: ref
+
additionalProperties: false
examples:
--
2.34.1
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