linux-kernel - Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

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Message-ID: <CAOX2RU4j57H51ceYdKk9K-2ZNO7N4MDA6BOKrP2N3DNbphQAow@mail.gmail.com>
Date:   Tue, 29 Aug 2023 13:18:07 +0200
From:   Robert Marko <robimarko@...il.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc:     Gokul Sriram Palanisamy <quic_gokulsri@...cinc.com>,
        agross@...nel.org, andersson@...nel.org, konrad.dybcio@...aro.org,
        mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, jassisinghbrar@...il.com,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        quic_varada@...cinc.com, quic_srichara@...cinc.com
Subject: Re: [PATCH 3/3] arm64: dts: qcom: ipq5018: enable the CPUFreq support

On Tue, 29 Aug 2023 at 13:10, Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> On 29/08/2023 12:56, Robert Marko wrote:
> >
> > On 29. 08. 2023. 12:12, Krzysztof Kozlowski wrote:
> >> On 29/08/2023 11:54, Gokul Sriram Palanisamy wrote:
> >>> Add the APCS, A53 PLL, cpu-opp-table nodes to set
> >>> the CPU frequency at optimal range.
> >>>
> >>> Co-developed-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> >>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@...cinc.com>
> >>> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@...cinc.com>
> >>> ---
> >>>   arch/arm64/boot/dts/qcom/ipq5018.dtsi | 34 +++++++++++++++++++++++++++
> >>>   1 file changed, 34 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >>> index 9f13d2dcdfd5..05843517312c 100644
> >>> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> >>> @@ -8,6 +8,7 @@
> >>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >>>   #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> >>>   #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> >>> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> >> c is before r.
> >>
> >>>
> >>>   / {
> >>>     interrupt-parent = <&intc>;
> >>> @@ -36,6 +37,8 @@ CPU0: cpu@0 {
> >>>                     reg = <0x0>;
> >>>                     enable-method = "psci";
> >>>                     next-level-cache = <&L2_0>;
> >>> +                   clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >>> +                   operating-points-v2 = <&cpu_opp_table>;
> >>>             };
> >>>
> >>>             CPU1: cpu@1 {
> >>> @@ -44,6 +47,8 @@ CPU1: cpu@1 {
> >>>                     reg = <0x1>;
> >>>                     enable-method = "psci";
> >>>                     next-level-cache = <&L2_0>;
> >>> +                   clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
> >>> +                   operating-points-v2 = <&cpu_opp_table>;
> >>>             };
> >>>
> >>>             L2_0: l2-cache {
> >>> @@ -54,6 +59,17 @@ L2_0: l2-cache {
> >>>             };
> >>>     };
> >>>
> >>> +   cpu_opp_table: opp-table-cpu {
> >>> +           compatible = "operating-points-v2";
> >>> +           opp-shared;
> >>> +
> >>> +           opp-1008000000 {
> >>> +                   opp-hz = /bits/ 64 <1008000000>;
> >>> +                   opp-microvolt = <1100000>;
> >>> +                   clock-latency-ns = <200000>;
> >> And the rest of OPPs?
> > Hi Krzysztof,
> > IPQ5018 only supports running at 1.1GHz, but its running at 800MHz
> > by default from the bootloader so there is only one OPP.
>
> Isn't this contradictory? If it is running at 800 initially, then it
> supports running at 800...

I can only guess that it's not validated at 800MHz.

Regards,
Robert
>
>
> Best regards,
> Krzysztof
>