linux-kernel - Re: [PATCH v12 0/6] Add non-coherent DMA support for AX45MP

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-Id: <169342742844.1913.17058276691232129949.git-patchwork-notify@kernel.org>
Date:   Wed, 30 Aug 2023 20:30:28 +0000
From:   patchwork-bot+linux-riscv@...nel.org
To:     Prabhakar <prabhakar.csengg@...il.com>
Cc:     linux-riscv@...ts.infradead.org, arnd@...db.de,
        conor.dooley@...rochip.com, geert+renesas@...der.be,
        guoren@...nel.org, ajones@...tanamicro.com,
        paul.walmsley@...ive.com, palmer@...belt.com,
        aou@...s.berkeley.edu, samuel@...lland.org, hch@...radead.org,
        emil.renner.berthing@...onical.com, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
        biju.das.jz@...renesas.com, prabhakar.mahadev-lad.rj@...renesas.com
Subject: Re: [PATCH v12 0/6] Add non-coherent DMA support for AX45MP

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@...osinc.com>:

On Fri, 18 Aug 2023 14:57:17 +0100 you wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> 
> Hi All,
> 
> non-coherent DMA support for AX45MP
> ====================================
> 
> [...]

Here is the summary with links:
  - [v12,1/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list
    https://git.kernel.org/riscv/c/93e0e2419b65
  - [v12,2/6] riscv: errata: Add Andes alternative ports
    https://git.kernel.org/riscv/c/f2863f30d1b0
  - [v12,3/6] riscv: mm: dma-noncoherent: nonstandard cache operations support
    https://git.kernel.org/riscv/c/30bc090f40f8
  - [v12,4/6] dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller
    https://git.kernel.org/riscv/c/555dd72bc06e
  - [v12,5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core
    https://git.kernel.org/riscv/c/f508b0175578
  - [v12,6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
    https://git.kernel.org/riscv/c/ed1a8872ff83

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html