linux-kernel - Re: [PATCH V5 1/6] scsi: ufs: qcom: Update offset for core_clk_1us

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Message-ID: <5bfd0788-d9a5-40e9-225d-a5f6bbd80c29@quicinc.com>
Date:   Wed, 30 Aug 2023 23:07:09 +0530
From:   Nitin Rawat <quic_nitirawa@...cinc.com>
To:     Manivannan Sadhasivam <mani@...nel.org>
CC:     <agross@...nel.org>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <jejb@...ux.ibm.com>,
        <martin.petersen@...cle.com>, <quic_cang@...cinc.com>,
        <quic_nguyenb@...cinc.com>, <linux-scsi@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
        "Naveen Kumar Goud Arepalli" <quic_narepall@...cinc.com>
Subject: Re: [PATCH V5 1/6] scsi: ufs: qcom: Update offset for
 core_clk_1us_cycles

On 8/28/2023 1:08 PM, Manivannan Sadhasivam wrote:
> On Wed, Aug 23, 2023 at 09:14:08PM +0530, Nitin Rawat wrote:
>> This Patch updates offset for core_clk_1us_cycles in DME_VS_CORE_CLK_CTRL
> 
> Please do not use "This patch" in commit message. Just reword it in imperative
> form.

Thanks Mani for the review. We Will address the commit text in next 
patchset.

-Nitin


> 
>> register. Offset for core_clk_1us_cycles is changed from Qualcomm UFS
>> Controller V4.0.0 onwards.
>>
>> Co-developed-by: Naveen Kumar Goud Arepalli <quic_narepall@...cinc.com>
>> Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@...cinc.com>
>> Signed-off-by: Nitin Rawat <quic_nitirawa@...cinc.com>
>> ---
>>   drivers/ufs/host/ufs-qcom.c | 19 ++++++++++++++-----
>>   drivers/ufs/host/ufs-qcom.h |  2 ++
>>   2 files changed, 16 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index f88febb23123..1108b0cd43b3 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -1297,12 +1297,21 @@ static void ufs_qcom_exit(struct ufs_hba *hba)
>>   }
>>
>>   static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
>> -						       u32 clk_cycles)
>> +						       u32 clk_1us_cycles)
> 
> How about "cycles_in_1us", since this value specifies "Number of clk cycles in
> 1us"?
I Will take care of this in next patchset

-Nitin

> 
>>   {
>> -	int err;
>> +	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
>> +	u32 mask = DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
>>   	u32 core_clk_ctrl_reg;
>> +	u32 offset = 0;
>> +	int err;
>> +
>> +	/* Bit mask and offset changed on UFS host controller V4.0.0 onwards */
> 
> This is not offset value, but rather shift. Still, if you use bitfield macros
> as I suggested below, you could get rid of this variable.

I Will take care of this in next patchset

-Nitin

> 
>> +	if (host->hw_ver.major >= 4) {
>> +		mask = MAX_CORE_CLK_1US_CYCLES_MASK_V4;
>> +		offset = MAX_CORE_CLK_1US_CYCLES_OFFSET_V4;
>> +	}
>>
>> -	if (clk_cycles > DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK)
>> +	if (clk_1us_cycles > mask)
>>   		return -EINVAL;
> 
> 	if (!FIELD_FIT(mask, cycles_in_1us))
> 		return -ERANGE;
> 
>>
>>   	err = ufshcd_dme_get(hba,
>> @@ -1311,8 +1320,8 @@ static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
>>   	if (err)
>>   		return err;
>>
>> -	core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK;
>> -	core_clk_ctrl_reg |= clk_cycles;
>> +	core_clk_ctrl_reg &= ~(mask << offset);
>> +	core_clk_ctrl_reg |= clk_1us_cycles << offset;
>>
> 
> 	core_clk_ctrl_reg &= ~mask;
> 	core_clk_ctrl_reg |= FIELD_PREP(mask, cycles_in_1us);
> 
>>   	/* Clear CORE_CLK_DIV_EN */
>>   	core_clk_ctrl_reg &= ~DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT;
>> diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
>> index d6f8e74bd538..a829296e11bb 100644
>> --- a/drivers/ufs/host/ufs-qcom.h
>> +++ b/drivers/ufs/host/ufs-qcom.h
>> @@ -129,6 +129,8 @@ enum {
>>   #define PA_VS_CONFIG_REG1	0x9000
>>   #define DME_VS_CORE_CLK_CTRL	0xD002
>>   /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
> 
>> +#define MAX_CORE_CLK_1US_CYCLES_MASK_V4		0xFFF
> 
> #define MAX_CORE_CLK_1US_CYCLES_MASK_V4				GENMASK(27, 16)
> #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK	GENMASK(7, 0)
> 
> - Mani


I will update it. Thanks
-Nitin

> 
>> +#define MAX_CORE_CLK_1US_CYCLES_OFFSET_V4	0x10
>>   #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT		BIT(8)
>>   #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK	0xFF
>>
>> --
>> 2.17.1
>>
>