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Message-Id: <20230830-topic-8550_dmac2-v1-7-49bb25239fb1@linaro.org>
Date: Wed, 30 Aug 2023 14:48:46 +0200
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Abel Vesa <abel.vesa@...aro.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Sai Prakash Ranjan <quic_saipraka@...cinc.com>,
Vinod Koul <vkoul@...nel.org>
Cc: Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, dmaengine@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@...aro.org>
Subject: [PATCH 7/7] arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent
In a fairly new development, Qualcomm somehow made the DWC3 block
cache-coherent. Annotate that.
Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@...aro.org>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 8ee61c9383ec..95ba9a9ac78e 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2944,6 +2944,7 @@ usb_1_dwc3: usb@...0000 {
snps,usb2-lpm-disable;
snps,has-lpm-erratum;
tx-fifo-resize;
+ dma-coherent;
ports {
#address-cells = <1>;
--
2.42.0
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