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Message-ID: <cec9318c-9a70-4392-89b7-048d30b7b790@linaro.org>
Date:   Wed, 30 Aug 2023 14:32:14 +0200
From:   Konrad Dybcio <konrad.dybcio@...aro.org>
To:     Komal Bajaj <quic_kbajaj@...cinc.com>, agross@...nel.org,
        andersson@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
        srinivas.kandagatla@...aro.org, bryan.odonoghue@...aro.org
Cc:     linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v8 4/6] soc: qcom: Add LLCC support for multi channel DDR

On 30.08.2023 12:56, Komal Bajaj wrote:
> Add LLCC support for multi channel DDR configuration
> based on a feature register.
> 
> Signed-off-by: Komal Bajaj <quic_kbajaj@...cinc.com>
> ---
[...]

global pointer to a error code to avoid referencing it */
> @@ -1031,6 +1050,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>  	const struct qcom_llcc_config *cfg;
>  	const struct llcc_slice_config *llcc_cfg;
>  	u32 sz;
> +	u8 cfg_index;
>  	u32 version;
>  	struct regmap *regmap;
> 
> @@ -1052,7 +1072,10 @@ static int qcom_llcc_probe(struct platform_device *pdev)
>  		ret = -EINVAL;
>  		goto err;
>  	}
> -	cfg = &cfgs->llcc_config[0];
This is unnecessary, get_cfg_index returns 0 when no nvmem cell is
present.

Konrad

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