[<prev] [next>] [day] [month] [year] [list]
Message-Id: <b29d870e7190aadebb18de7e40d8306c28568156.1693407232.git.geert+renesas@glider.be>
Date: Wed, 30 Aug 2023 16:54:58 +0200
From: Geert Uytterhoeven <geert+renesas@...der.be>
To: Russell King <linux@...linux.org.uk>,
Arnd Bergmann <arnd@...db.de>,
Linus Walleij <linus.walleij@...aro.org>
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Geert Uytterhoeven <geert+renesas@...der.be>
Subject: [PATCH] ARM: Kconfig: Spelling s/Cortex A-/Cortex-A/
Fix a misspelling of "Cortex-A9", to make it easier to find which errata
are applicable to Cortex-A9 CPU cores.
Signed-off-by: Geert Uytterhoeven <geert+renesas@...der.be>
---
arch/arm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7a27550ff3c1f817..029b40f8a39e380d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -818,7 +818,7 @@ config ARM_ERRATA_764319
bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
depends on CPU_V7
help
- This option enables the workaround for the 764319 Cortex A-9 erratum.
+ This option enables the workaround for the 764319 Cortex-A9 erratum.
CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
unexpected Undefined Instruction exception when the DBGSWENABLE
external pin is set to 0, even when the CP14 accesses are performed
--
2.34.1
Powered by blists - more mailing lists