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Message-ID: <AS8PR04MB8676B511250439EF71D0E3488CE6A@AS8PR04MB8676.eurprd04.prod.outlook.com>
Date: Wed, 30 Aug 2023 07:31:24 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
"vkoul@...nel.org" <vkoul@...nel.org>,
"kishon@...nel.org" <kishon@...nel.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
"conor+dt@...nel.org" <conor+dt@...nel.org>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
"festevam@...il.com" <festevam@...il.com>,
"l.stach@...gutronix.de" <l.stach@...gutronix.de>,
"a.fatoum@...gutronix.de" <a.fatoum@...gutronix.de>,
"u.kleine-koenig@...gutronix.de" <u.kleine-koenig@...gutronix.de>
CC: "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kernel@...gutronix.de" <kernel@...gutronix.de>,
dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH v1 1/3] dt-bindings: phy: Add i.MX8QM PCIe PHY binding
Hi Krzsztof:
Thanks for your review.
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Sent: 2023年8月29日 15:48
> To: Hongxing Zhu <hongxing.zhu@....com>; vkoul@...nel.org;
> kishon@...nel.org; robh+dt@...nel.org; krzysztof.kozlowski+dt@...aro.org;
> conor+dt@...nel.org; shawnguo@...nel.org; s.hauer@...gutronix.de;
> festevam@...il.com; l.stach@...gutronix.de; a.fatoum@...gutronix.de;
> u.kleine-koenig@...gutronix.de
> Cc: linux-phy@...ts.infradead.org; devicetree@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org;
> kernel@...gutronix.de; dl-linux-imx <linux-imx@....com>
> Subject: Re: [PATCH v1 1/3] dt-bindings: phy: Add i.MX8QM PCIe PHY binding
>
> On 29/08/2023 08:45, Richard Zhu wrote:
> > Add i.MX8QM PCIe PHY binding.
> >
> > i.MX8QM HSIO(High Speed IO) module has three instances of single lane
> > SERDES PHYs, an instance of two lanes PCIe GEN3 controller, an
> > instance of single lane PCIe GEN3 controller, as well as an instance
> > of SATA 3.0 controller.
> >
> > The HSIO module can be configured as the following different usecases.
> > 1 - A two lanes PCIea and a single lane SATA.
> > 2 - A single lane PCIea, a single lane PCIeb and a single lane SATA.
> > 3 - A two lanes PCIea, a single lane PCIeb.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> > ---
> > .../bindings/phy/fsl,imx8-pcie-phy.yaml | 70 ++++++++++++++++++-
> > 1 file changed, 67 insertions(+), 3 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > index 182a219387b0..764790f2b10b 100644
> > --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
> > @@ -17,16 +17,18 @@ properties:
> > enum:
> > - fsl,imx8mm-pcie-phy
> > - fsl,imx8mp-pcie-phy
> > + - fsl,imx8qm-pcie-phy
> >
> > reg:
> > maxItems: 1
> >
> > clocks:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 5
> >
> > clock-names:
> > - items:
> > - - const: ref
> > + minItems: 1
> > + maxItems: 5
> >
> > resets:
> > minItems: 1
> > @@ -70,6 +72,36 @@ properties:
> > description: PCIe PHY power domain (optional).
> > maxItems: 1
> >
> > + hsio-cfg:
>
> Missing vendor prefix because it does not look like generic property.
Okay, would add the fsl,hsio- prefix later.
>
> > + description: |
> > + Specifies the different usecases supported by the HSIO(High
> > + Speed IO)
>
> I don't know what are the usecases...
Sorry, miss one space between "use" and "cases".
i.MX8QM HSIO module can be controlled by DSC/software in these three
different modes. So I add this property (fsl,hsio-cfg) here to specify the
work mode of HSIO.
>
> > + module. PCIEAX2SATA means two lanes PCIea and a single lane SATA.
> > + PCIEAX1PCIEBX1SATA represents a single lane PCIea, a single lane
> > + PCIeb and a single lane SATA. PCIEAX2PCIEBX1 on behalf of a two
> > + lanes PCIea, a single lane PCIeb.
> > + Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants to
> > + be used (optional).
>
> None of all this helped me to understand what part of hardware this is responsible
> for. It seems you just want to program a register, but instead you should use one
> of existing properties like phy-modes etc.
It's my bad. Didn't describe the HW clearly above.
The fsl,hsio-cfg is used to specify the work mode of HSIO subsystem, not only
the PHY mode. Since the PHYs are contained in the HSIO subsystem, can't be
used by PCIe or SATA controller freely. The usage of these PHYs are limited
by the HSIO work modes. BTW, up to now, I still don't have a good idea to
describe the HSIO by phy-modes property although I prefer this way in my mind.
>
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [ 1, 2, 3 ]
> > +
> > + ctrl-csr:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle to the ctrl-csr region containing the HSIO control and
> > + status registers for PCIe or SATA controller (optional).
>
> Please try some internal review before posting to patches. Community is not cheap
> reviewers taking this duty from NXP. I am pretty sure NXP can afford someone
> looking at the code.
>
> This misses vendor prefix, as explained many times for every syscon phandle. Also
> optional is redundant.
Sorry about the missing prefix. The prefix would be added later.
And the optional would be removed. Thanks.
>
> But anyway status of PCIe or SATA controller is not a property of the phy, so it
> looks to me you stuff here some properties belonging to some other missing
> devices.
I see. You're right the status of PCIe or SATA controller is not a property
of the PHY. Some bits contained in the ctrl-csr region, are used to kick
off resets through the internal glue logic. So, this property is added
for phy driver.
>
> > +
> > + misc-csr:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle to the misc-csr region containing the HSIO control and
> > + status registers for misc (optional).
>
> Same problems.
>
"fsl,hsio-" prefix would be added later.
> > +
> > + phy-csr:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description:
> > + phandle to the phy-csr region containing the HSIO control and
> > + status registers for phy (optional).
>
> Same problems.
"fsl,hsio-" prefix would be added later.
>
>
> > +
> > required:
> > - "#phy-cells"
> > - compatible
> > @@ -78,6 +110,38 @@ required:
> > - clock-names
> > - fsl,refclk-pad-mode
> >
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + enum:
> > + - fsl,imx8qm-pcie-phy
> > + then:
> > + properties:
> > + clocks:
> > + minItems: 4
> > + maxItems: 5
> > + clock-names:
> > + oneOf:
> > + - items:
> > + - const: pipe_pclk
> > + - const: ctrl_ips_clk
> > + - const: phy_ips_clk
> > + - const: misc_ips_clk
>
> Drop clk everywhere.
Sorry, would be changed and aligned later.
> > + - items:
> > + - const: apb_pclk
>
> No, optional clock goes to the end and please explain why APB is optional.
I understand that phy should have the apb_pclk whatever it is used in
which mode. Would keep aligned in the clock definitions later. Thanks.
Best Regards
Richard Zhu
>
>
>
> Best regards,
> Krzysztof
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