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Message-Id: <20230830-fp5-initial-v1-1-5a954519bbad@fairphone.com>
Date: Wed, 30 Aug 2023 11:58:26 +0200
From: Luca Weiss <luca.weiss@...rphone.com>
To: cros-qcom-dts-watchers@...omium.org,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Viresh Kumar <viresh.kumar@...aro.org>
Cc: ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-pm@...r.kernel.org, Luca Weiss <luca.weiss@...rphone.com>
Subject: [PATCH 01/11] arm64: dts: qcom: sc7280: Mark some nodes as
'reserved'
With the standard Qualcomm TrustZone setup, components such as lpasscc,
pdc_reset and watchdog shouldn't be touched by Linux. Mark them with
the status 'reserved' and reeable them in the chrome-common dtsi.
Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>
---
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 12 ++++++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 ++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
index 2e1cd219fc18..8eb30aa226a2 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
@@ -46,6 +46,14 @@ wpss_mem: memory@...00000 {
};
};
+&lpasscc {
+ status = "okay";
+};
+
+&pdc_reset {
+ status = "okay";
+};
+
/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
&pmk8350_pon {
status = "disabled";
@@ -84,6 +92,10 @@ &scm {
dma-coherent;
};
+&watchdog {
+ status = "okay";
+};
+
&wifi {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 042908048d09..98a8d627a348 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2267,6 +2267,7 @@ lpasscc: lpasscc@...0000 {
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
+ status = "reserved";
};
lpass_rx_macro: codec@...0000 {
@@ -4216,6 +4217,7 @@ pdc_reset: reset-controller@...0000 {
compatible = "qcom,sc7280-pdc-global";
reg = <0 0x0b5e0000 0 0x20000>;
#reset-cells = <1>;
+ status = "reserved";
};
tsens0: thermal-sensor@...3000 {
@@ -5212,11 +5214,12 @@ msi-controller@...40000 {
};
};
- watchdog@...10000 {
+ watchdog: watchdog@...10000 {
compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ status = "reserved";
};
timer@...20000 {
--
2.42.0
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